Cirrus Logic CS4525, Manual

Page: 26 / 98

26 DS726PP2
CS4525
6. APPLICATIONS
6.1 Software Mode
Maximum device flexibility and features are available when the CS4525 is used in software mode. The avail-
able features are described in the following sections. All device configuration is achieved via the I²C control
port as described in the
I²C Control Port Description and Timing section on page 64 .
6.1.1 System Clocking
In software mode, the CS4525 can be clocked by a stable external clock source input on the SYS_CLK
pin or by a clock internally generated through the use of its internal oscillator driver circuit in conjunction
with an external crystal oscillator. The device automatically selects which of these clocks to use within
10 ms of the release of RST.
The internal clock is used to synchronize the input serial audio signals with the internal clock domain and
to clock the internal digital processing, sample-rate converter, and PWM modulators. It is also used to de-
termine the sample rate of the serial audio input signals in order to automatically configure the various
internal filter coefficients.
To ensure proper operation, the CS4525 must be informed of the nominal frequency of the supplied
SYS_CLK signal or the attached crystal via the ClkFreq[1:0] bits in the Clock Config register. These bits
must be set to the appropriate value before the PDnAll bit is cleared to initiate a power-up sequence. See
the
SYS_CLK Switching Specifications and XTI Switching Specifications tables on page 23 for complete
input frequency range specifications.
WARNING: The system clock source must never be removed or stopped while any of the power output
stages are powered-up (the PDnAll bit and any of the PDnOut1, PDnOut2, or PDnOut3/4 bits are cleared)
and connected to a load. Doing so may result in permanent damage to the CS4525 and connected trans-
ducers.
6.1.1.1 SYS_CLK Input Clock Mode
If an input clock is detected on the SYS_CLK pin following the release of RST, the device will automatically
use the SYS_CLK input as its clock source. The applied SYS_CLK clock signal must oscillate within the
frequency ranges specified in the SYS_CLK switching specifications table on
page 23 . In this mode, XTI
should be connected to ground and XTO should be left unconnected.
Figure 12 below demonstrates a typical clocking configuration using the SYS_CLK input.
Referenced Control Register Location
ClkFreq[1:0]......................... “Clock Frequency (ClkFreq[1:0])” on page 69
PDnAll ................................. “Power Down (PDnAll)” on page 89
PDnOutX ............................. “Power Down PWM Power Output X (PDnOutX)” on page 88
SYS_CLK
RST
DSP
Reset_Out
Clock_In
Clock
XTI
XTO
Figure 12. Typical SYS_CLK Input Clocking Configuration
CS4525