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Cirrus Logic CS4265, Manual

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DS657F3

CS4265

6.3.1 DAC Digital Interface Format (Bits 5:4) ................................................................................. 37

6.3.2 Mute DAC (Bit 2)  ................................................................................................................... 37

6.3.3 De-Emphasis Control (Bit 1) .................................................................................................. 38

6.4 ADC Control - Address 04h ............................................................................................................ 38

6.4.1 Functional Mode (Bits 7:6)  .................................................................................................... 38

6.4.2 ADC Digital Interface Format (Bit 4) ...................................................................................... 38

6.4.3 Mute ADC (Bit 2)  ................................................................................................................... 39

6.4.4 ADC High-Pass Filter Freeze (Bit 1)  ..................................................................................... 39

6.4.5 Master / Slave Mode (Bit 0) ................................................................................................... 39

6.5 MCLK Frequency - Address 05h  .................................................................................................... 39

6.5.1 Master Clock Dividers (Bits 6:4) ............................................................................................ 39

6.6 Signal Selection - Address 06h  ...................................................................................................... 40

6.6.1 DAC SDIN Source (Bit 7)  ...................................................................................................... 40

6.6.2 Digital Loopback (Bit 1)  ......................................................................................................... 40

6.7 Channel B PGA Control - Address 07h  .......................................................................................... 40

6.7.1 Channel B PGA Gain (Bits 5:0) ............................................................................................. 40

6.8 Channel A PGA Control - Address 08h  .......................................................................................... 40

6.8.1 Channel A PGA Gain (Bits 5:0) ............................................................................................. 40

6.9 ADC Input Control - Address 09h  ................................................................................................... 41

6.9.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3)  .................................................................. 41

6.9.2 Analog Input Selection (Bit 0) ................................................................................................ 41

6.10 DAC Channel A Volume Control - Address 0Ah ........................................................................... 41

6.11 DAC Channel B Volume Control - Address 0Bh ........................................................................... 42

6.11.1 Volume Control (Bits 7:0)  .................................................................................................... 42

6.12 DAC Control 2 - Address 0Ch  ...................................................................................................... 42

6.12.1 DAC Soft Ramp or Zero Cross Enable (Bits 7:6)  ................................................................ 42

6.12.2 Invert DAC Output (Bit 5)  .................................................................................................... 43

6.13 Status - Address 0Dh  ................................................................................................................... 43

6.13.1 E to F C-Buffer Transfer ...................................................................................................... 43

6.13.2 Clock Error (Bit 3) ................................................................................................................ 43

6.13.3 ADC Overflow (Bit 1) ........................................................................................................... 43

6.13.4 ADC Underflow (Bit 0) ......................................................................................................... 43

6.14 Status Mask - Address 0Eh  .......................................................................................................... 44

6.15 Status Mode MSB - Address 0Fh ................................................................................................. 44

6.16 Status Mode LSB - Address 10h  .................................................................................................. 44

6.17 Transmitter Control 1 - Address 11h  ............................................................................................ 44

6.17.1 E to F C-Data Buffer Transfer Inhibit (Bit 6)  ........................................................................ 44

6.17.2 C-Data Access Mode (Bit 5) ................................................................................................ 44

6.18 Transmitter Control 2 - Address 12h  ............................................................................................ 45

6.18.1 Transmitter Digital Interface Format (Bits 7:6)  .................................................................... 45

6.18.2 Transmitter Output Driver Control (Bit 5) ............................................................................. 45

6.18.3 Transmitter Mute Control (Bit 4) .......................................................................................... 45

6.18.4 Transmitted Validity Bit Control (Bit 3)  ................................................................................ 45

6.18.5 Transmitter Mono/Stereo Operation Control (Bit 2) ............................................................. 45

6.18.6 Mono Mode CS Data Source (Bit 1) .................................................................................... 45

6.18.7 Mono Mode Channel Selection (Bit 0) ................................................................................. 46

7. PARAMETER DEFINITIONS ................................................................................................................ 47
8. DAC FILTER PLOTS         .................................................................................................................... 48
9. ADC FILTER PLOTS    ......................................................................................................................... 50
10. EXTERNAL IEC60958-3 TRANSMITTER COMPONENTS  ............................................................... 52

10.1 IEC60958-3 Transmitter External Components ............................................................................ 52

10.2 Isolating Transformer Requirements  ............................................................................................ 52

11. CHANNEL STATUS BUFFER MANAGEMENT  ................................................................................ 53

11.1 IEC60958-3 Channel Status (C) Bit Management ........................................................................ 53

Summary of Contents for CS4265

Page 1: ...ifferential Stereo Line Inputs Stereo Microphone Inputs 32 dB Gain Stage Low Noise Bias Supply Up to 192 kHz Sampling Rates Selectable Serial Audio Interface Formats Left Justified up to 24 bit I S up to 24 bit High Pass Filter or DC Offset Calibration 1 8 V to 5 V Multibit Modulator Multibit Modulator Low Latency Anti Alias Filter Interpolation Filter Interpolation Filter Left DAC Output Right DA...

Page 2: ...r atten uation of 12 dB in 0 5 dB steps The output of the PGA is followed by an advanced 5th order multi bit delta sigma modulator and digital filter ing decimation Sampled data is transmitted by the serial audio interface at rates from 4 kHz to 192 kHz in either Slave or Master Mode The D A converter is based on a 4th order multi bit delta sigma modulator with an ultra linear low pass filter and ...

Page 3: ...log Input Multiplexer PGA and Mic Gain 27 4 5 Input Connections 27 4 5 1 Pseudo Differential Input 27 4 6 Output Connections 28 4 7 Output Transient Control 28 4 7 1 Power Up 28 4 7 2 Power Down 28 4 7 3 Serial Interface Clock Changes 28 4 8 DAC Serial Data Input Multiplexer 29 4 9 De Emphasis Filter 29 4 10 Internal Digital Loopback 29 4 11 Mute Control 30 4 12 AES3 Transmitter 30 4 12 1 TxOut Dr...

Page 4: ...6 12 1 DAC Soft Ramp or Zero Cross Enable Bits 7 6 42 6 12 2 Invert DAC Output Bit 5 43 6 13 Status Address 0Dh 43 6 13 1 E to F C Buffer Transfer 43 6 13 2 Clock Error Bit 3 43 6 13 3 ADC Overflow Bit 1 43 6 13 4 ADC Underflow Bit 0 43 6 14 Status Mask Address 0Eh 44 6 15 Status Mode MSB Address 0Fh 44 6 16 Status Mode LSB Address 10h 44 6 17 Transmitter Control 1 Address 11h 44 6 17 1 E to F C D...

Page 5: ...6 Control Port Timing I C Read 32 Figure 17 De Emphasis Curve 38 Figure 18 DAC Single Speed Stopband Rejection 48 Figure 19 DAC Single Speed Transition Band 48 Figure 20 DAC Single Speed Transition Band 48 Figure 21 DAC Single Speed Passband Ripple 48 Figure 22 DAC Double Speed Stopband Rejection 48 Figure 23 DAC Double Speed Transition Band 48 Figure 24 DAC Double Speed Transition Band 49 Figure ...

Page 6: ...e Revision 36 Table 6 Freeze able Bits 36 Table 7 DAC Digital Interface Formats 37 Table 8 De Emphasis Control 38 Table 9 Functional Mode Selection 38 Table 10 ADC Digital Interface Formats 39 Table 11 MCLK Frequency 39 Table 12 DAC SDIN Source Selection 40 Table 13 Example Gain and Attenuation Settings 40 Table 14 PGA Soft Cross or Zero Cross Mode Selection 41 Table 15 Analog Input Selection 41 T...

Page 7: ...al Ground Input Ground reference for the analog line inputs AFILTA AFILTB 10 11 Antialias Filter Connection Output Antialias filter connection for the ADC inputs VQ 12 Quiescent Voltage Output Filter connection for internal quiescent voltage FILT 13 Positive Voltage Reference Output Positive reference voltage for the internal sampling circuits MICIN1 MICIN2 14 15 Microphone Input Input The full sc...

Page 8: ...Data Input Input Input for two s complement serial audio data SDIN2 24 Serial Audio Data Input 2 Input Input for two s complement serial audio data SDIN1 25 Serial Audio Data Input 1 Input Input for two s complement serial audio data SDOUT 26 Serial Audio Data Output Output Output for two s complement serial audio data SCLK 27 Serial Clock Input Output Serial clock for the serial audio interface L...

Page 9: ... will not cause SCR latch up Parameters Symbol Min Nom Max Units DC Power Supplies Analog Digital Logic Serial Port Logic Control Port VA VD VLS VLC 3 13 3 13 1 71 1 71 5 0 3 3 3 3 3 3 5 25 Note 1 5 25 5 25 V V V V Ambient Operating Temperature Power Applied TA 10 70 C Parameter Symbol Min Max Units DC Power Supplies Analog Digital Logic Serial Port Logic Control Port VA VD VLS VLC 0 3 0 3 0 3 0 3...

Page 10: ...o 24 Bit A Weighted unweighted 16 Bit A Weighted unweighted 98 95 90 87 104 101 96 93 96 93 88 85 104 101 96 93 dB dB dB dB Total Harmonic Distortion Noise Note 4 18 to 24 Bit 0 dB 20 dB 60 dB 16 Bit 0 dB 20 dB 60 dB THD N 90 81 41 93 73 33 84 87 90 81 41 93 73 33 82 85 dB dB dB dB dB dB Dynamic Performance for VA 3 13 V to 3 46 V Dynamic Range Note 4 18 to 24 Bit A Weighted unweighted 16 Bit A We...

Page 11: ...res 18 to 27 have been normalized to Fs and can be de normalized by multiplying the X axis scale by Fs Parameter Note 7 10 Symbol Min Typ Max Unit Combined Digital and On chip Analog Filter Response Single Speed Mode Passband Note 7 to 0 1 dB corner to 3 dB corner 0 0 0 35 0 4992 Fs Fs Frequency Response 10 Hz to 20 kHz 0 175 0 01 dB StopBand 0 5465 Fs StopBand Attenuation Note 8 50 dB Group Delay...

Page 12: ...DS657F3 CS4265 AOUTx AGND 3 3µF V out R L C L Figure 1 DAC Output Test Load Figure 2 Maximum DAC Loading 100 50 75 25 2 5 5 10 15 Safe Operating Region Capacitive Load C pF L Resistive Load R k L 125 3 20 ...

Page 13: ...101 98 98 95 92 dB dB dB dB dB dB Total Harmonic Distortion Noise Note 12 PGA Setting 12 dB to 6 dB 1 dB 20 dB 60 dB Note 13 40 kHz bandwidth 1 dB PGA Setting 12 dB Gain 1 dB 20 dB 60 dB Note 13 40 kHz bandwidth 1 dB THD N 95 81 41 92 92 75 35 89 89 86 dB dB dB dB dB dB dB dB Dynamic Performance for VA 3 13 V to 3 46 V Dynamic Range PGA Setting 12 dB to 6 dB A weighted unweighted Note 13 40 kHz ba...

Page 14: ...le Input Voltage 0 51 VA 0 57 VA 0 63 VA Vpp Input Impedance Note 11 6 12 6 8 7 48 k Maximum Interchannel Input Impedance Mismatch 5 Line Level and Microphone Level Inputs Parameter Symbol Commercial Grade Unit Min Typ Max DC Accuracy Interchannel Gain Mismatch 0 1 dB Programmable Gain Characteristics Gain Step Size 0 5 dB Absolute Gain Step Error 0 4 dB ...

Page 15: ... Total Harmonic Distortion Noise Note 12 PGA Setting 12 dB to 0 dB 1 dB 20 dB 60 dB PGA Setting 12 dB 1 dB THD N 80 60 20 68 74 dB dB dB dB Dynamic Performance for VA 3 13 V to 3 46 V Dynamic Range PGA Setting 12 dB to 0 dB A weighted unweighted PGA Setting 12 dB A weighted unweighted 77 74 65 62 83 80 71 68 dB dB dB dB Total Harmonic Distortion Noise Note 12 PGA Setting 12 dB to 0 dB 1 dB 20 dB 6...

Page 16: ...pple 0 035 dB Stopband 0 5688 Fs Stopband Attenuation 70 dB Total Group Delay Fs Output Sample Rate tgd 12 Fs s Double Speed Mode Passband 0 1 dB 0 0 4896 Fs Passband Ripple 0 025 dB Stopband 0 5604 Fs Stopband Attenuation 69 dB Total Group Delay Fs Output Sample Rate tgd 9 Fs s Quad Speed Mode Passband 0 1 dB 0 0 2604 Fs Passband Ripple 0 025 dB Stopband 0 5000 Fs Stopband Attenuation 60 dB Total...

Page 17: ...ng capacitors Parameter Symbol Min Typ Max Unit Power Supply Current VA 5 V Normal Operation VA 3 3 V VD VLS VLC 5 V VD VLS VLC 3 3 V IA IA ID ID 41 37 39 23 50 45 47 28 mA mA mA mA Power Supply Current VA 5 V Power Down Mode Note 18 VLS VLC VD 5 V IA ID 0 50 0 54 mA mA Power Consumption Normal Operation VA VD VLS VLC 5 V VA VD VLS VLC 3 3 V Power Down Mode VA VD VLS VLC 5 V 400 198 4 2 485 241 mW...

Page 18: ...ge VL 1 71 V Serial Port Control Port VL 2 0 V Serial Port Control Port VIH VIH VIH VIH 0 8xVLS 0 8xVLC 0 7xVLS 0 7xVLC V V V V Low Level Input Voltage Serial Port Control Port VIL VIL 0 2xVLS 0 2xVLC V V High Level Output Voltage at Io 2 mA Serial Port Control Port MUTEC TXOUT VOH VOH VOH VOH VLS 1 0 VLC 1 0 VA 1 0 VD 1 0 V V V V Low Level Output Voltage at Io 2 mA Serial Port Control Port MUTEC ...

Page 19: ...ter Mode LRCK Duty Cycle 50 SCLK Duty Cycle 50 SCLK falling to LRCK edge tslr 10 10 ns SCLK falling to SDOUT valid tsdo 0 36 ns SDIN valid to SCLK rising setup time tsdis 16 ns SCLK rising to SDIN hold time tsdih 20 ns Slave Mode LRCK Duty Cycle 40 50 60 SCLK Period Single Speed Mode Double Speed Mode Quad Speed Mode tsclkw tsclkw tsclkw ns ns ns SCLK Pulse Width High tsclkh 30 ns SCLK Pulse Width...

Page 20: ...slr t SDOUT SCLK Output LRCK Output SDIN sdo t sdih t sdis t slr t SDOUT SCLK Input LRCK Input SDIN sdo t sdih t sclkh t sclkl t sclkw t Figure 3 Master Mode Serial Audio Port Timing Figure 4 Slave Mode Serial Audio Port Timing ...

Page 21: ...ight LSB LSB MSB Figure 6 Format 1 I S up to 24 Bit Data LRCK SCLK SDATA 3 2 1 5 4 MSB 1 2 3 4 5 3 2 1 5 4 1 2 3 4 Channel A Left Channel B Right LSB MSB LSB LRCK SCLK SDATA 5 4 3 2 1 1 2 3 4 5 5 4 3 2 1 1 2 3 4 5 6 6 6 6 Channel A Left Channel B Right MSB LSB MSB LSB LSB Figure 7 Format 2 Right Justified 16 Bit Data Format 3 Right Justified 24 Bit Data ...

Page 22: ...ior to first clock pulse thdst 4 0 µs Clock Low time tlow 4 7 µs Clock High Time thigh 4 0 µs Setup Time for Repeated Start Condition tsust 4 7 µs SDA Hold Time from SCL Falling Note 24 thdd 0 µs SDA Setup time to SCL Rising tsud 250 ns Rise Time of SCL and SDA Note 25 trc trd 1 µs Fall Time SCL and SDA Note 25 tfc tfd 300 ns Setup Time for Stop Condition tsusp 4 7 µs Acknowledge Delay from SCL Fa...

Page 23: ...3 µF 10 k 10 k C Rext Rext See Note 2 AIN1A Left Analog Input 1 10 µF 10 µF 1800 pF 1800 pF 100 k 100 k 100 100 AIN1B Right Analog Input 1 10 µF 10 µF 10 µF Note 1 Resistors are required for I C control port operation For best response to Fs 2 470 4 470 ext ext R Fs R C This circuitry is intended for applications where the CS4265 connects directly to an unbalanced output of the design For internal...

Page 24: ... are clocked into or out of the device The FM bits See Functional Mode Bits 7 6 on page 38 and the MCLK Freq bits See MCLK Frequency Address 05h on page 39 configure the device to generate the proper clocks in Master Mode and receive the proper clocks in Slave Mode Table 2 illustrates several standard audio sample rates andthe required MCLK and LRCK frequencies Mode Sampling Frequency Single Speed...

Page 25: ...must be synchronously derived from the master clock MCLK and be equal to 128x 64x 48x or 32x Fs depending on the desired speed mode Refer to Table 4 for required clock ra tios 4 3 High Pass Filter and DC Offset Calibration When using operational amplifiers in the input circuitry driving the CS4265 a small DC offset may be driven into the A D converter The CS4265 includes a high pass filter after t...

Page 26: ... value of the DC offset for the each channel is frozen and this DC offset will continue to be subtracted from the conversion result This feature makes it possible to perform a system DC offset cal ibration by 1 Running the CS4265 with the high pass filter enabled until the filter settles See the ADC Digital Filter Characteristics section for filter settling time 2 Disabling the high pass filter an...

Page 27: ...alog modulator samples the input at 6 144 MHz MCLK 12 288 MHz The digital filter will reject sig nals within the stopband of the filter However there is no rejection for input signals which are n 6 144 MHz the digital passband frequency where n 0 1 2 Refer to the Typical Connection Diagram for the recommended analog input circuit that will attenuate noise energy at 6 144 MHz The use of capac itors...

Page 28: ...TB are clamped to VQ which is initially low After the PDN bit is released set to 0 the outputs begin to ramp with VQ towards the nominal quiescent voltage This ramp takes approximately 200 ms to complete The gradual voltage ramping allows time for the external DC blocking capacitors to charge to VQ effectively blocking the qui escent DC voltage Audio output will begin after approximately 2000 samp...

Page 29: ...page 38 for de em phasis control The de emphasis feature is included to accommodate audio recordings that utilize 50 15 s pre emphasis equalization as a means of noise reduction De emphasis is only available in Single Speed Mode 4 10 Internal Digital Loopback The CS4265 supports an internal digital loopback mode in which the output of the ADC is routed to the input of the DAC This mode may be acti...

Page 30: ...s and transmits audio and digital data according to the IEC60958 3 S PDIF interface standard The transmitter receives audio data from the input pin TXSDIN and control clocks from the PCM Serial Interface Audio and control data are multiplexed together and bi phase mark encoded The resulting bit stream is driven from the output pin TXOUT to an output connector either directly or through a transform...

Page 31: ... I C Control Port Description and Timing The control port is used to access the registers allowing the CS4265 to be configured for the desired oper ational modes and formats The operation of the control port may be completely asynchronous with respect to the audio sample rates However to avoid potential interference problems the control port pins should remain static if no operation is required SD...

Page 32: ...n the status register as listed in the status register descriptions See Status Address 0Dh on page 43 Each source may be masked off through mask register bits In addition each source may be set to rising edge falling edge or level sensitive Combined with the option of level sensitive or edge sensitive modes within the mi crocontroller many different configurations are possible depending on the nee...

Page 33: ...er clock This will ensure that all converters begin sampling on the same clock edge 4 17 Grounding and Power Supply Decoupling As with any high resolution converter the CS4265 requires careful attention to power supply and grounding arrangements if its po tential performance is to b e realized Figure 9 shows the recommended power ar rangements with VA connected to a clean supply VD which powers th...

Page 34: ...served Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0 0 0 0 0 0 0 0 0 08h PGA Ch A Gain Control Reserved Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0 0 0 0 0 0 0 0 0 09h Analog Input Control Reserved Reserved Reserved PGASoft PGAZero Reserved Reserved Select 0 0 0 1 1 0 0 1 0Ah DAC Ch A Vol ume Control Vol7 Vol6 Vol5 Vol4 Vol3 Vol2 Vol1 Vol0 0 0 0 0 0 0 0 0 0Bh DAC Ch B Vol ume Control Vol7 Vol6 Vol...

Page 35: ...er Control 1 Reserved EFTCI CAM Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 0 12h Transmitter Control 2 Tx_DIF1 Tx_DIF0 TxOff TxMute V MMT MMTCS MMTLR 0 0 0 0 0 0 0 0 13h 2Ah C Data Buffer Addr Function 7 6 5 4 3 2 1 0 ...

Page 36: ...eously set the Freeze bit make all changes then clear the Freeze bit The bits affected by the Freeze function are listed in Table 6 6 2 2 Power Down MIC Bit 3 Function The microphone preamplifier block will enter a low power state whenever this bit is set 6 2 3 Power Down ADC Bit 2 Function The ADC pair will remain in a reset state whenever this bit is set 7 6 5 4 3 2 1 0 PART3 PART2 PART1 PART0 R...

Page 37: ...face Format and the options are detailed in Table 7 and Figures 5 7 6 3 2 Mute DAC Bit 2 Function The DAC outputs will mute and the MUTEC pin will become active when this bit is set Though this bit is active high it should be noted that the MUTEC pin is active low The common mode voltage on the outputs will be retained when this bit is set The muting function is effected similar to attenuation cha...

Page 38: ...The required relationship between LRCK SCLK and SDOUT is defined by the ADC Digital Interface For mat bit The options are detailed in Table 10 and may be seen in Figure 5 and Figure 6 DeEmph Description 0 Disabled default 1 44 1 kHz de emphasis Table 8 De Emphasis Control 7 6 5 4 3 2 1 0 FM1 FM0 Reserved ADC_DIF Reserved MuteADC HPFFreeze M S FM1 FM0 Mode 0 0 Single Speed Mode 4 to 50 kHz sample r...

Page 39: ...slave operation for the serial audio port Setting this bit selects Master Mode while clearing this bit selects Slave Mode 6 5 MCLK Frequency Address 05h 6 5 1 Master Clock Dividers Bits 6 4 Function Sets the frequency of the supplied MCLK signal See Table 11 for the appropriate settings ADC_DIF Description Format Figure 0 Left Justified up to 24 bit data default 0 5 1 I S up to 24 bit data 1 6 Tab...

Page 40: ...Gain Bits 5 0 Function Sets the gain or attenuation for the ADC input PGA stage The gain may be adjusted from 12 dB to 12 dB in 0 5 dB steps The gain bits are in two s complement with the Gain0 bit set for a 0 5 dB step Register settings outside of the 12 dB range are reserved and must not be used See Table 13 for ex ample settings 7 6 5 4 3 2 1 0 SDINSel Reserved Reserved Reserved Reserved Reserv...

Page 41: ... Zero Cross Enable dictate that signal level changes either by attenuation changes or mut ing will occur in 1 8dB steps and be implemented on asignal zero crossing The 1 8 dB level change will occur after a time out period between 512 and 1024 sample periods 10 7 ms to 21 3 ms at 48 kHz sam ple rate if the signal does not encounter a zero crossing The zero cross function is independently mon itore...

Page 42: ...Enable Zero Cross Enable dictates that signal level changes either by attenuation changes or muting will occur on a signal zero crossing to minimize audible artifacts The requested level change will occur after a time out period between 512 and 1024 sample periods 10 7 ms to 21 3 ms at 48 kHz sample rate if the signal does not encounter a zero crossing The zero cross function is independently moni...

Page 43: ...l always be 0 in this register Thisregister defaults to 00h 6 13 1 E to F C Buffer Transfer Function Indicates the completion of an E to F C buffer transfer See Channel Status Buffer Management on page 53 for more information 6 13 2 Clock Error Bit 3 Function Indicates the occurrence of a clock error condition 6 13 3 ADC Overflow Bit 1 Function Indicates the occurrence of an ADC overflow condition...

Page 44: ...status bit be comes active on the removal of the condition In Level Active Mode the status bit is active during the condition 00 Rising edge active 01 Falling edge active 10 Level active 11 Reserved 6 17 Transmitter Control 1 Address 11h 6 17 1 E to F C Data Buffer Transfer Inhibit Bit 6 Function When cleared C data E to F buffer transfers are allowed When set C data E to F buffer transfers are in...

Page 45: ...ndicated When this bit is set invalid or non linear PCM audio data is indicated 6 18 5 Transmitter Mono Stereo Operation Control Bit 2 Function When this bit is cleared the transmitter will operate in stereo mode When set the transmitter will operate in Mono Mode with one input channel s data output in both A and B subframes see IEC60958 3 Channel Status C Bit Management on page 53 and the CS data...

Page 46: ...election Bit 0 Function When this bit is cleared channel A input data will be transmitted in both channel A and B subframes in mono mode When this bit is set channel B input data will be transmitted in both channel A and B sub frames in Mono Mode ...

Page 47: ...s Total Harmonic Distortion Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth typically 10 Hz to 20 kHz including distortion components Expressed in decibels Measured at 1 and 20 dBFS as suggested in AES17 1991 Annex A Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the ampli...

Page 48: ...5 0 5 0 25 0 2 0 15 0 1 0 05 0 0 05 Frequency normalized to Fs Amplitude dB Figure 20 DAC Single Speed Transition Band Figure 21 DAC Single Speed Passband Ripple 0 45 0 46 0 47 0 48 0 49 0 5 0 51 0 52 0 53 0 54 0 5 5 10 9 8 7 6 5 4 3 2 1 0 Frequency normalized to Fs Amplitude dB Figure 22 DAC Double Speed Stopband Rejection Figure 23 DAC Double Speed Transition Band ...

Page 49: ...Quad Speed Stopband Rejection Figure 27 DAC Quad Speed Transition Band 0 35 0 4 0 45 0 5 0 55 0 6 0 65 0 7 0 75 60 50 40 30 20 10 0 Amplitude dB Frequency normalized to Fs 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 100 90 80 70 60 50 40 30 20 10 0 Amplitude dB Frequency normalized to Fs 0 0 05 0 1 0 15 0 2 0 25 0 3 0 35 0 4 0 45 0 5 1 5 1 0 5 0 Frequency normalized to Fs Amplitude dB Figure 28 DAC Qu...

Page 50: ... 100 90 80 70 60 50 40 30 20 10 0 0 40 0 42 0 44 0 46 0 48 0 50 0 52 0 54 0 56 0 58 0 60 Frequency normalized to Fs Amplitude dB 10 9 8 7 6 5 4 3 2 1 0 0 45 0 46 0 47 0 48 0 49 0 5 0 51 0 52 0 53 0 54 0 55 Frequency normalized to Fs Amplitude dB 0 10 0 08 0 06 0 04 0 02 0 00 0 02 0 04 0 06 0 08 0 10 0 0 05 0 1 0 15 0 2 0 25 0 3 0 35 0 4 0 45 0 5 Frequency normalized to Fs Amplitude dB 140 130 120 ...

Page 51: ...0 0 05 0 10 0 15 0 20 0 25 0 30 0 35 0 40 0 45 0 50 Frequency normalized to Fs Amplitude dB 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 Frequency normalized to Fs Amplitude dB 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 0 20 0 25 0 30 0 35 0 40 0 45 0 50 0 55 0 60 0 65 0 70 0 75 0 80 0 85 Frequency normalized to Fs Amplitude dB 10 9 8 7 6 5 4 3...

Page 52: ...s of 243 in place of the 374 resistor and a 107 resistor in place of the 90 9 resistor The standard connector for a consumer application is an RCA phono socket The TXOUT pin may be used to drive TTL or CMOS gates as shown in Figure 43 This circuit may be used for optical connectors for digital audio as they typically implement TTL or CMOS compatible inputs This cir cuit is also useful when driving...

Page 53: ...rmation are buffered at the input synchronized to the output time base and then transmitted The buffering scheme involves a cascade of two block sized buffers named E and F as shown in Figure 44 The MSB of each byte represents the first bit in the serial C data stream For example the MSB of byte 0 which is at control port address 13h is the consumer professional bit for channel status block A The ...

Page 54: ...he user sets this bit This may be used whenever long control port interactions are occurring A flowchart for reading and writing to the E buffer is shown in Figure 45 For writing the sequence starts after an E to F transfer which is based on the output time base 11 2 Serial Copy Management System SCMS The CS4265 allows read modify write access to all the channel status bits For consumer mode SCMS ...

Page 55: ...ocations in the addressed word One Byte Mode saves the user substantial control port access time as it effectively accesses two byte s worth of information in 1byte s worth of access time If the control port s auto increment addressing is used in combination with this mode multi byte accesses such as full block reads or writes can be done espe cially efficiently 11 3 2 Two Byte Mode There are thos...

Page 56: ... 05 1 b 0 0071 0 0091 0 0110 0 18 0 23 0 28 1 2 D 0 1969 BSC 5 00 BSC 1 D2 0 1280 0 1299 0 1319 3 25 3 30 3 35 1 E 0 1969 BSC 5 00 BSC 1 E2 0 1280 0 1299 0 1319 3 25 3 30 3 35 1 e 0 0197 BSC 0 50 BSC 1 L 0 0118 0 0157 0 0197 0 30 0 40 0 50 1 JEDEC MO 220 Controlling Dimension is Millimeters Parameters Symbol Min Typ Max Units Package Thermal Resistance 2 Layer Board 4 Layer Board JA 52 38 C Watt C...

Page 57: ...g those pertaining to warranty indemnification and limitation of liability No responsibility is assumed by Cirrus for the use of this information including use of this information as the basis for manufacture or sale of any items or for infringement of patents or other rights of third parties This document is the property of Cirrus and by furnishing this information Cirrus grants no license expres...

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