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CDB4954A/55A

8

J34

GND Jumper for Dig Video 
Input

Jumpered

Open

Gnd Connected
No Gnd Connect

J3

J13
J15
J17
J20
J21
J22
J23
J24
J25
J27
J29
J31

High/Low Impedance Select

NOTE: All Jumpers must be in 
the same position, namely 
High or Low.  Also, only 
change impedance loading 
with the power off.

High

Low

High Impedance
Low Impedance

S1

DIP Switch for Stand Alone 
Mode

(See 

Table 3

)

(See 

Table 3

)

S2

Reset Switch

-

Resets the 
CDB4954A/55A

Table 2. CBD4954 Jumper/Switch Settings (Continued)

Switch

Purpose

Position

Function Selected

8

Clipping Input Signals

ON

OFF

Clipping On
Clipping Off (CS4954 Con Reg 6, bit 6)

7

Pedestal Offset

ON

OFF

Pedestal Offset = 7.5 IRE
Pedestal Offset = 0 IRE (CS4954 Con Reg 1, bit 1)

6

NTSC/PAL Format

ON

OFF

PAL-B Mode
NTSC-M Mode 

5

Not  Used

-

-

1-4

Operating Modes
NOTE: OFF = 0 

ON = 1

0000
1000
0100

1100

0010
1010

0110

1110

0001
1001
0101

1101
0011
1011

Display Color Bars (70% Amp, 70% Sat)
Display Luma Bars (70% Amp, 70% Sat)
Display a Luma Step
Display an Aqua Screen
Display a Luma Ramp (1 bit/2 pixels)
Display a Luma Ramp (1 bit/ pixel)
Display a Luma Ramp (2 bit/ pixel)
Display a Luma Ramp (4 bit/ pixel)
Select Parallel Video Input as External Source
Select Serial Video Input as External Source
Display Video from Flash Block 1 (Cirrus Logo - NTSC)
Display Video from Flash Block 2 (Cirrus Logo - PAL)
Display Video from Flash Block 3

Select the D656 Bus Header(J32) as external video 
input source

.

Table 3. DIP Switch Settings

Summary of Contents for Crystal SDB4954A

Page 1: ...xternal TTL level timing and data signals for use during system development Also to simplify the demonstration of the features of the CS4954 the CDB4954A 55A is equipped with an on board microcontroller and pre programmed FLASH memory to facilitate configuration and evaluation of the CS4954 digital video encoder ORDERING INFORMATION CDB4954A Evaluation Board CDB4955A Evaluation Board I Regulator M...

Page 2: ...rovision Corporation Preliminary product information describes products which are in production but for which full characterization data is not yet available Advance product infor mation describes products which are in development and subject to development changes Cirrus Logic Inc has made best efforts to ensure that the information contained in this document is accurate and reliable However the ...

Page 3: ...CDB4954A 55A 3 LIST OF TABLES Table 1 System Connections 7 Table 2 CBD4954 Jumper Switch Settings 7 Table 3 DIP Switch Settings 8 ...

Page 4: ...the supplied 9 pin serial cable to connect your IBM PC or compatible to the 9 pin D Sub connector labeled J6 RS 232 on the CDB4954A 55A 2 1 DIP Switch Options If you use the CDB4954A 55A Evaluation Board without a PC i e in the standalone mode use the followings to set up the board using the 8 position dip switch The dip switch positions are marked 1 8 The individual switches select these function...

Page 5: ...720x480 pixels to CCIR656 PAL or NTSC files These converted files can then be downloaded to the FLASH on the evaluation board for storage and later replay or downloaded directly to SDRAM for immediate playing 2 2 2 1 Convert to CCIR656 File Option This option converts a bitmap image bmp file extension of up to 720x480 into a CCIR656 NTSC nts file extension or PAL pal file exten sion file This step...

Page 6: ...gister Val ues tab This allows FPGA registers to be manipu lated directly Note that the FPGA Register is NOT part of the CS4954 55 m This parameter shows the Macrovision Reg isters tabs if a CS4955 is in place on the CDB4954A 55A Evaluation Board If a CS4954 is in place on the board the Macrovision Registers tabs are not shown since the CS4954 doesn t have Macrovision support whether or not the m ...

Page 7: ...ial Video Input J26 Input Output RS232 Interface Table 1 System Connections Header Switch Purpose Jumper Position Function Selected J2 Voltage Supply Select 3 3V 5V 3 3 V Operation 5 V Operation J5 J7 Output Test Point for Serial Receiver Testpoints J6 Phase Sensor Output Testpoints J8 FPGA Program Debug Header Testpoints J9 Flash Write Enable Jumpered Open Write Enabled Write Not Enabled J10 Test...

Page 8: ...stal Offset ON OFF Pedestal Offset 7 5 IRE Pedestal Offset 0 IRE CS4954 Con Reg 1 bit 1 6 NTSC PAL Format ON OFF PAL B Mode NTSC M Mode 5 Not Used 1 4 Operating Modes NOTE OFF 0 ON 1 0000 1000 0100 1100 0010 1010 0110 1110 0001 1001 0101 1101 0011 1011 Display Color Bars 70 Amp 70 Sat Display Luma Bars 70 Amp 70 Sat Display a Luma Step Display an Aqua Screen Display a Luma Ramp 1 bit 2 pixels Disp...

Page 9: ...CDB4954A 55A 9 Figure 5 Digital Video Input ...

Page 10: ...CDB4954A 55A 10 Figure 6 FPGA ...

Page 11: ...CDB4954A 55A 11 Figure 7 CS4954 5 ...

Page 12: ...CDB4954A 55A 12 Figure 8 Microprocessor ...

Page 13: ...CDB4954A 55A 13 Figure 9 Video Output Filters ...

Page 14: ...CDB4954A 55A 14 Figure 10 Power RS232 Interface ...

Page 15: ...CDB4954A 55A 15 Figure 11 Silkscreen Top ...

Page 16: ...CDB4954A 55A 16 Figure 12 Top Side ...

Page 17: ...CDB4954A 55A 17 Figure 13 Power Layer ...

Page 18: ...CDB4954A 55A 18 Figure 14 Ground Layer ...

Page 19: ...CDB4954A 55A 19 Figure 15 Bottom Side ...

Page 20: ......

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