DS723DB1
7
CDB43L21
2. SOFTWARE MODE CONTROL
The CDB43L21 may be used with the Microsoft
®
Windows-based FlexGUI graphical user interface, allowing soft-
ware control of the CS43L21 and FPGA registers. The latest control software may be downloaded from
. Step-by-step instructions for setting up the FlexGUI are provided as follows:
1.
Download and install the FlexGUI software according to the instructions provided on the Website.
2.
Connect and apply power to the +5.0 V binding post.
3.
Connect the CDB to the host PC using either a 9-pin serial or USB cable.
4.
Launch the Cirrus FlexGUI.
Once the GUI is launched successfully, all registers are set to their default reset
state.
5.
Enable the CS43L21 by engaging the “Enable CS43L21” push-button.
6.
Refresh the GUI by clicking on the “Update” button.
The default state of all registers are now visible.
7.
Engage and then disengage the “Power Down” push-button in the “General Configurations” group.
This per-
forms the necessary write sequence to the
CS43L21
for Software Mode operation.
For standard setup:
8.
Set up the signal routing in the “General Configurations” tab as desired.
9.
Set up the CS43L21 in the “General Configurations” and “DAC Volume Controls” tab as desired.
10. Begin evaluating the CS43L21.
For quick setup,
the CDB43L21 may be configured by loading a predefined sample script file:
11. On the File menu, click "Restore Board Registers..."
12. Browse to Boards\CDB43L21\Scripts\.
13. Choose any one of the provided scripts to begin evaluation.
To create personal scripts files:
14. On the File menu, click "Save Board Registers..."
15. Enter any name that sufficiently describes the created setup.
16. Choose the desired location and save the script.
17. To load this script, follow the instructions from step
above.
Summary of Contents for CDB43L21
Page 16: ...16 DS723DB1 CDB43L21 7 CS43L21 SCHEMATICS Figure 10 CS43L21 and Analog I O Schematic Sheet 1 ...
Page 17: ...DS723DB1 17 CDB43L21 Figure 11 S PDIF I O Schematic Sheet 2 ...
Page 18: ...18 DS723DB1 CDB43L21 Figure 12 FPGA Schematic Sheet 3 ...
Page 19: ...DS723DB1 19 CDB43L21 Figure 13 Level Shifters I O Stake Header Schematic Sheet 4 ...
Page 20: ...20 DS723DB1 CDB43L21 Figure 14 Control Port I O Schematic Sheet 5 ...
Page 21: ...DS723DB1 21 CDB43L21 Figure 15 Power Schematic Sheet 6 ...
Page 22: ...22 DS723DB1 CDB43L21 8 CDB43L21 LAYOUT Figure 16 Silk Screen CDB43L21 CS43L21 CS43L21 CS43L21 ...
Page 23: ...DS723DB1 23 CDB43L21 Figure 17 Top Side Layer ...
Page 24: ...24 DS723DB1 CDB43L21 Figure 18 Bottom Side Layer ...
