24
DS77
3DB1
CDB42L55
7 CDB42L55 BLOCK DIAGRAM
Figure 36. Block Diagram
USB
Serial
PC Control
Board Power
External 5.0 V
Supply
LDO’s
Buck
(not included)
1.8 V
2.5 V
3.3 V
1.8 V
CS42L55
FPGA
24 MHz
Oscillator
Clock/Data Routing
Clock dividers and PLL used
to derive all applicable Fs
from 24 MHz oscillator
PLL
I²C for all
applicable
devices
LDO
VL, VCP, VLDO, VA
MUX
3.3 V (VL only)
Circuit Break for
External System
Interface
PCM
Clocks/Data
I²C Clocks/
Data
I/O Stake Headers for Audio
Precision’s Programmable Serial
Interface Adapter (PSIA)
I/O SMA Connectors
for External System
Interface
Tri-state
Buffers
SRC (Rx)
SRC (Tx)
S/PDIF Rx
S/PDIF Tx
Stereo
Input 1
Stereo
Input 2
Stereo HP
Output
Stereo Line
Output
HP
Jack
x3
AAA Alkaline
CODEC Power
Summary of Contents for CDB42L55
Page 25: ...DS773DB1 25 CDB42L55 8 CDB42L55 SCHEMATICS Figure 37 CS42L55 Analog I O Schematic Sheet 1 ...
Page 26: ...26 DS773DB1 CDB42L55 Figure 38 S PDIF Digital Interface Schematic Sheet 2 ...
Page 27: ...DS773DB1 27 CDB42L55 Figure 39 PLL oscillator and external I O connections Schematic Sheet 3 ...
Page 28: ...28 DS773DB1 CDB42L55 Figure 40 Microcontroller and FPGA Schematic Sheet 4 ...
Page 29: ...DS773DB1 29 CDB42L55 Figure 41 Power Schematic Sheet 5 ...
Page 30: ...30 DS773DB1 CDB42L55 9 CDB42L55 LAYOUT Figure 42 Silk Screen ...
Page 31: ...DS773DB1 31 CDB42L55 Figure 43 Top Side Layer ...
Page 32: ...32 DS773DB1 CDB42L55 Figure 44 GND Layer 2 ...
Page 33: ...DS773DB1 33 CDB42L55 Figure 45 Power Layer 3 ...
Page 34: ...34 DS773DB1 CDB42L55 Figure 46 Bottom Side Layer ...
Page 35: ...DS773DB1 35 CDB42L55 10 REVISION HISTORY Revision Changes DB1 Initial Release ...
