BGS3 Hardware Interface Description
2.3 Circuit Concept
21
BGS3_HD_v01.000d
Page 21 of 109
2010-03-26
Confidential / Released
2.3
Circuit Concept
shows a block diagram of the BGS3 module and illustrates the major functional com-
ponents:
Baseband block:
•
Digital baseband processor with DSP
•
Analog processor with power supply unit (PSU)
•
Flash / PSRAM (stacked)
•
Application interface (SMT with connecting pads)
RF section:
•
RF transceiver
•
RF power amplifier
•
RF front
•
Antenna pad
Figure 2:
BGS3
block diagram
BATT+
GND
IGT
EMERG_OFF
ASC(0)
SIM Interface
D(0:15)
A(0:24)
RD; WR; CS; WAIT
Interface
RF - Baseband
NTC
BATT_TEMP
SYNC
RF
Transceiver
RF
Power Amplifier
PSRAM
Nor-Flash
Audio analog
VEXT
ISENSE
VSENSE
VCHARGE
CHARGEGATE
TEMP1
REFCHG
ASC(1)
26MHz
RF
Front End
PWR_IND
Measuring
Network
32.768
kHz
26MHz
App
lic
atio
n In
te
rf
ac
e
Digital and Analog
Baseband Processor
TEMP2
BATTEMP
Several
Power supply
voltages
DAI