CHAINTECH CT-9PJL, User Manual

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Appendix
Appendix
Digidoc 80-Port POST Error Code List
POST (hex) Description
CF Test CMOS R/W functionality.
C0
Early chipset initialization:
-Disable shadow RAM
-Disable L2 cache (socket 7 or below)
-Program basic chipset registers.
C1
Detect memory:
-Auto-detection of DRAM size, type and ECC.
-Auto-detection of L2 cache (socket 7 or below)
C3
Expand compressed BIOS code to DRAM.
C5
Call chipset hook to copy BIOS back to E000 & F000 shadow RAM.
01
Expand the Xgroup codes locating in physical address 1000:0
03 Initial Superio_Early_Init switch.
05
Blank out screen.
Clear CMOS error flag.
07
Clear 8042 interface.
Initialize 8042 self-test.
08
Test special keyboard controller for Winbond 977 series Super I/O
chips.
Enable keyboard interface.
0A
Disable PS/2 mouse interface (optional).
Auto detects ports for keyboard & mouse followed by a port & interface
swap (optional).
Reset keyboard for Winbond 977 series Super I/O chips.
0E
Test F000h segment shadow to see whether it is R/W-able or not. If test
fails, keep beeping the speaker.
10
Auto detect flash type to load appropriate flash R/W codes into the run
time area in F000 for ESCD & DMI support.
12
Use walking 1’s algorithm to check out interface in CMOS circuitry.
Also set real-time clock power status, and then check for override.
14
Program chipset default values into chipset. Chipset default values are
MODBINable by OEM customers.
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