— 24 —
10-7. Operation program ROM pin discriptions (
µ
PD23C4001EBGW-304)
10-8. RAM pin discriptions (M5M51008AFP-10LL)
Pin No.
Name
In/Out
Status
Status
Description
of OFF
of ON
2~12,23,
A0~A18
In
L
Pulse
Address bus line (A0~A14, RA15~RA18)
25~31
13~15, 17~21
O0~O7
Out
L
Pulse
Data bus line (IO0~IO7)
16
GND
In
L
L
GND terminal
22
CEB
In
H
Pulse
Chip enable signal from Gate array
24
OEB
In
L
Pulse
Output enable signal from Gate array
1, 32
N.C., VCC
In
L
H
VDD terminal
Pin No.
Name
In/Out
Status
Status
Description
of OFF
of ON
2~12,23,
A0~A16
In
L
Pulse
Address bus line (A0~A14, RA15, RA16)
25~28, 31
13~15, 17~21
O0~O7
Out
L
Pulse
Data bus line (IO0~IO7)
16
GND
In
L
L
GND terminal
22
CS1
In
H
Pulse
Chip enable signal from Gate array
24
OEB
In
L
Pulse
Output enable signal from Gate array
1, 32
N.C., VCC
In
L
H
VDD terminal
29
WEB
In
H
Pulse
Write enable signal from CPU
Summary of Contents for SF-8500
Page 1: ...SF 8500 LX 575 AUG 1993 R without price INDEX...
Page 3: ...1 1 SCHEMATIC DIAGRAM 1 1 Main PCB...
Page 4: ...2 1 2 Display PCB...
Page 5: ...3 1 3 Key Matrix...
Page 34: ...33 13 PARTS LIST SF 8500...
Page 35: ...34...
Page 36: ...35 14 PCB VIEW...
Page 37: ...37 15 ASSEMBLY VIEW...
Page 38: ...8 11 10 Nishi Shinjuku Shinjuku ku Tokyo 160 Japan Telephone 03 3347 4926...
