Cardin Elettronica MORPH433W01, Manual

Page: 23 / 52

23
Frame make up for the WIEGAND signals
The frame in the
WIEGAND
format is emitted by means of the
DATA0
and
DATA1
signals. The dura-
tion of each single bit is 50μs while the waiting period between one bit and the next is 2 ms.
The frame leaving the interface is formed of 16 characters. Each
character is made up of 5 bits according to the table on the left,
where the most significant bit is
B4
, and the least significant is
B1 .
The parity bit is odd parity for B4 , B3 , B2 , B1 .
The frame is as follows: START + CHANNEL (1 character) + SEP
+ CODE (10 characters) + SEP + END + LRC, i.e. 16 characters
altogether.
Frame construction exampl e limited to six characters; transmitting the code " 452 "
At the end of the frame an LRC control character is sent which
is calculated by working out the even parity longitudinally along
the corresponding bits as shown in the table on the left.
The first bit out is
B1 and the last one out is the parity bit.
Frame composition diagrams for ISO2 signals
There are three ISO2 signals: CLS (Card Loading Signal), RCP (Read Clock Pulse) and RDP (Read
Data Pulse). The 3 signals are active low.
First of all the
CLS
drops and after 5 ms 10 clock pulse are sent; the data packet is then sent and
then their is a pause of 5ms before pulling up the CLS .
Parity B4 B3 B2 B1 Character
1 0 0 0 0 0
0 0 0 0 1 1
0 0 0 1 0 2
1 0 0 1 1 3
0 0 1 0 0 4
1 0 1 0 1 5
1 0 1 1 0 6
0 0 1 1 1 7
0 1 0 0 0 8
1 1 0 0 1 9
0 1 0 1 1 START
0 1 1 0 1 SEP
0 1 1 1 1 END
CLS
5ms
RCP
RDP
5ms
MEANING BIT PARITY
Start 1 0 1 1 0
"4" 0 1 0 0 0
"5" 0 1 0 1 1
"2" 0 0 1 1 0
End 1 1 1 1 1
LRC 0 1 1 1 0
1
0
1
DATA 1
2mS
DATA 0
ISO2 PROTOCOL (BIT FLOW SEQUENCE)