Canoga Perkins 2240, User Manual, Page: 50 / 106

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Canoga Perkins
4.4 RS-530 Interface Model 430
NOTE: The -430 interface supersedes the previous -R30 interface for
2240 applications. The -430 interface is a superset of the -R30. If
exact
compatibility with the older -R30 is desired, the DCD jumper can be
moved from the factory strapped CTRL setting (end-to-end RTS-DCD
control lead pair always enabled) to CD (DCD function selected by
main board CD / DCD and CD / SYNC switches).
This interface conforms to EIA RS-530. The interface uses RS-422 (balanced)
electrical signals for all interface circuits (data, clock and control), except for the
loopback and test mode pins which use RS-423 (unbalanced bipolar) electrical
signals. Jumper options are detailed in the following sections. The DB-25 pin
assignments and signals supported are detailed in Table 4-C.
The interface connector is a female DB-25 with a separate 3.5 mm stereo phone jack
that can be used as an alarm contact input. Refer to Section 2.2.3 for more informa-
tion on configuring the alarm contact input.
The TD, RD, SCT, SCR and SCTE pins carry the primary data and clock signals
(conforming to the RS-449 and RS-422 standards). In addition, the SCT leads can
be reversed via a switch to provide an extra clock signal input (conforming to RS-
422) to make the 2240 / -430 combination more DTE-like in tail circuit applications
at the clock source (refer to Section 2.2.6). The remainder of the pins are either
ground references or control signals. Transmit Data (TD) and Receive Data (RD) are
the data input and output signals to the modem, respectively.
Serial Clock Transmit (SCT) is the modem’s transmit clock reference output that is
used for the internal and slave clock modes. Serial Clock Receive (SCR) is the clock
signal for the receive data
unless the 2240's main PCBA W26 (XTCLK) jumper is
ON, in which case the Extra Clock input signal is used to shift receive data out from
the 2240 (refer to Section 2.2.6). Serial Clock Transmit External (SCTE) is the
transmit clock signal used in either of the External Clock modes or when the main
board internal CLK/EXT switch is set to EXT (refer to Section 3.7).