MGentleLASE
Bubble Circuit Calibration Procedure
Candela Corporation
Page 4 of 5 Candela Corporation Proprietary 8503-01-0830, Revision A
the HP BBL is highlighted. Toggle the BBL Ckt Test off. Verify the voltage on the CPU
I/O PCB at TP30 (+) and TP31 (-) returns to 7.75 VDC
±
0.5 VDC.
12.
Connect the DVM to the Canister Bubble Sense Test Point on the CPU I/O PCB at
TP29 (+) and TP31 (-). Verify the voltage is 7.75 VDC
±
0.5 VDC. If not, remove the
Top skin cover and then adjust R1 of the Canister Bubble PCB to get 7.75VDC on the
DVM. The canister must be installed and the pressure above 115 PSI before
adjusting R1.
13.
Disconnect the cryogen line from the front panel bulkhead connector. Remove the
canister from the DCD Option Assembly. Wait 1 minute. Verify the voltage on the
CPU I/O PCB at TP29 (+) and TP31 (-) is greater than 10.50 VDC. Also verify that
the maintenance TOGGLE screen Can BBL is highlighted. Return the canister to the
DCD Option Assembly.
14.
Reconnect the cryogen line to the front panel bulkhead connector. Verify that within
two minutes, the TOGGLE screen Can BBL is not highlighted and the voltage on the
CPU I/O PCB at TP29 (+) and TP31 (-) returns to 7.75 VDC
±
0.5 VDC.
15.
In the maintenance screen toggle the BBL Ckt Test on and verify the voltage on the
CPU I/O PCB at TP29 (+) and TP31 (-) is greater than 10.50 VDC and the Can BBL
highlighted. Toggle the BBL Ckt Test off. Verify the voltage on the CPU I/O PCB at
TP29 (+) and TP31 (-) returns to 7.75 VDC
±
0.5 VDC.
16.
Reinstall cryogen line to the front panel bulkhead connector.
