Campbell SM4M, Instruction Manual

Page: 39 / 46

C-1
Appendix C. Storage Module 9-Pin
Connector
The pins on the 9-pin sub-miniature D connector on the Storage Module are
numbered 1 to 9. A general description of the function of each pin follows:
Pin 1 (Input) 5 VDC Supply provides power to the Storage Module.
5
±
0.3 VDC @ 100mA. Processor held in reset when external power
falls below 4 VDC. Damage to Storage Module hardware can occur if
input on Pin 1 exceeds 5.5 VDC. Low power standby mode current
drain is less than 200
µ
A.
Pin 2 (Input) Power and signal GROUND.
Pin 3 RING LINE. Not used.
Pin 4 (Output) RECEIVE DATA (RD) line. The Storage Module transmits
its responses to Telecommunications commands asynchronously (0 to 5
VDC) on this line. Data format is 8-bit, 1 start bit and 1 stop bit. Refer
to Section 3.1 for baud rate options. This line is held high while the
Storage Module is active in the Printer Enable Method (data storage).
Pin 5 MODEM ENABLE line. Not used.
Pin 6 (Input) PRINTER ENABLE (PE) in Printer Enable Method or
SYNCHRONOUS DEVICE ENABLE (SDE) line in SDC Method. If
the Storage Module is externally powered, the PE line is high (5 VDC)
and Pin 7 (CLK/HS) is low (0 VDC), the processor is set to receive data
asynchronously on Pin 9 (TD). When the PE line is dropped, data
remaining in the input buffer are stored and the location pointers are
saved. The processor then enters an inactive, low power, standby state.
If the processor is still active from a previous transmission of data and
the PE line is raised again, the data from the current transmission will
be ignored. Normal operation will return with the next low to high PE
transition. Switch bounce on the PE line can cause the processor to go
inactive after the PE line stabilizes in its high state.
Pin 7 (Input) CLOCK/HANDSHAKE (CLK/HS) line. For data storage,
CLK/HS must be low. For data retrieval using Telecommunications
Commands (see Appendix B) CLK/HS must be high when the
processor is activated by the PE line going high. CLK/HS must remain
high during Telecommunications. To exit the Telecommunications
Command State, lower both the PE and CLK/HS lines.
Pin 8 TAPE ENABLE / 12V power line. Not used.
Pin 9 (Input) TRANSMIT DATA (TD) Data is received by the Storage
Module on this line. Data is received asynchronously ( 0 to 5 VDC) 8-
bit, 1 start and 1 stop bit. The idle state (stop bits) on this line is 0
VDC. The first byte transmitted to the Storage Module should be more
than 200
µ
s after the PE line has activated the processor.