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CAES NOEL-PF-EX, User Manual

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CAES NOEL-PF-EX User Manual Download Page 7

NOEL-PF-EX-UM

Jul 2022, Version 2.0

7

NOEL-PF-EX

 

Cobham Gaisler AB

Kungsgatan | SE-411 19 | Goteborg | Sweden

+46 31 7758650 | www.caes.com/gaisler

ranges will receive an AHB error response. The detailed register layout is defined in the description of

each individual core.

Table 5.

AMBA AHB address range

Core

Address range

Area

L2CACHE
/ PFDDR4

0x00000000 - 0x3FFFFFFF

DDR4 SDRAM area

AHBROM

0xC0000000 - 0xC001FFFF

Registers

CLINT

0xE0000000 - 0xE000FFFF

Registers

PLIC

0xF8000000 - 0xFBFFFFFF

Registers

GPTIMER

0xFC000000 - 0xFC0000FF

Registers

APBUART0

0xFC001000 - 0xFC0010FF

Registers

GRVERSION

0xFC080000 - 0xFC0800FF

Registers

AHBSTAT

0xFC080200 - 0xFC0830FF

Registers

GRGPIO

0xFC083000 - 0xFC0830FF

Registers

AHBUART

0xFC086000 - 0xFC0860FF

Registers

Debug Module

0xFE000000 - 0xFEFFFFFF

Registers

L2CACHE IOAREA

0xFFF00000 - 0xFF3FFFFF

Registers

AHB plug&play

0xFFFFF000 - 0xFFFFFFFF

ROM area

Summary of Contents for NOEL-PF-EX

Page 1: ...C V standard PMP RISC V standard debug support Level 2 cache DDR4 SDRAM UART Timers GPIO port Status registers Ethernet 10 100 1000 Mbit MAC interface Description The NOEL PF FPGA bitstreams are a col...

Page 2: ...cument revision history 3 1 3 Reference documents 3 2 Example designs 4 2 1 Overview 4 2 2 Configurations 5 3 Architecture 6 3 1 Cores 6 3 2 Interrupts 6 3 3 Memory map 6 3 4 IP core documentation 8 3...

Page 3: ...Synopsys Synplify Premier This document describes ready made FPGA configurations bitstreams that have been built from a GRLIB template design More information about the NOEL V processor is available...

Page 4: ...following modules NOEL V RV32 with 16 KiB instruction cache and 16 KiB data cache Debug Support Unit with UART and JTAG Debug Links Level 2 cache controller Microsemi FDDR4 SDRAM controller Timer unit...

Page 5: ...not suitable for use in harsh environments Table 2 Example configurations Configuration name MC32L SC MC32 SC GP32 SC GP32F SC GP64F SC PolarFire Device MPF300T MPF300T MPF300T MPF300T MPF300T Process...

Page 6: ...ap The example designs use the same memory map for all standard configurations The memory map shown in table 5 is based on the AMBA AHB address space An access to addresses outside the Table 3 Used IP...

Page 7: ...0x00000000 0x3FFFFFFF DDR4 SDRAM area AHBROM 0xC0000000 0xC001FFFF Registers CLINT 0xE0000000 0xE000FFFF Registers PLIC 0xF8000000 0xFBFFFFFF Registers GPTIMER 0xFC000000 0xFC0000FF Registers APBUART...

Page 8: ...isler NOEL PF EX 3 4 IP core documentation This user manual does not contain IP core documentation Please refer to the GRLIB IP Core User s Manual GRIP available at http gaisler com products grlib gri...

Page 9: ...borg Sweden 46 31 7758650 www caes com gaisler 3 5 Signals Please see the NOEL PF EX Quick Start Guide QSG for information on FPGA pinout 3 6 Resource utilization Resource utilization is described in...

Page 10: ...he NOEL PF EX designs Toolchains and run time environments are available for download via http gaisler com 4 2 Programming the FPGA device and connecting with GRMON3 Please see the NOEL PF EX Quick St...

Page 11: ...2022 Version 2 0 11 Cobham Gaisler AB Kungsgatan SE 411 19 Goteborg Sweden 46 31 7758650 www caes com gaisler NOEL PF EX 5 Ordering information Please contact sales gaisler com for information on the...

Page 12: ...of the application or use of any product or service described herein except as expressly agreed to in writing by Cobham nor does the purchase lease or use of a product or service from Cobham convey a...

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