© Cobham Gaisler AB
Kungsgatan 12 | SE-411 19 Goteborg | Sweden
+46 31 7758650 | www.caes.com/gaisler
25
GR-CPCIS-XCKU
Document Data Sheet & User Manual
Feb 2022, Version 1.2
Figure 13
FPGA JTAG Interface
4.6.8
FPGA-GPIO
16 GPIO signals (SOCPIO[15..0]) are connected from the FPGA to a 20 pin header,
J9.
This allows accessory boards to be easily attached to the board with a short ribbon cable, to provide
additional IO functions. For example, connecting a
GR-ACC-6U-6UART
could provide 6 standard
serial UART interface, or a
GR-ACC-GR740
board could provide 2 UART, 2 CAN and a Dual 1553
interface, if the logic in the FPGA is appropriately configured.
Figure 14
FPGA-GPIO interface
These FPGA signals are LVCMOS18 voltage levels but in order to ensure compatibility with
accessory boards, 3V3 to1V8 translation buffers are included in the design. These Bi-directional
buffers exhibit an output impedance of about 4kOhm which may limit the achievable drive strength.
The interface signal to FPGA pin correspondence is listed in Table 10 .
Table 10
FPGA-GPIO (SOC_PIO) Interface to FPGA pin mapping
Interface
Signal
FPGA Bank
FPGA Signal
FPGA pin
FPGA-GPIO SOCPIO0
Bank 25
IO_L8P
AV38
SOCPIO1
Bank 25
IO_L4N
AW26
SOCPIO2
Bank 25
IO_L6N
AU35