CAES GR-CPCIS-XCKU, User Manual, Page: 19 / 56

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19
GR-CPCIS-XCKU
Document Data Sheet & User Manual
Feb 2022, Version 1.2
Interface Signal FPGA Bank FPGA Signal FPGA pin
TXD3 Bank 64 IO_L10N AP18
RXD0 Bank 64 IO_L16P AK18
RXD1 Bank 64 IO_L16N AK17
RXD2 Bank 64 IO_L15N AK16
RXD3 Bank 64 IO_L15P AJ16
TXCLK Bank 64 IO_L12P AM19
TX_CTL Bank 64 IO_L9N AM19
RXCLK Bank 64 IO_L14P Al19
RX_CTL Bank 64 IO_L9P AP16
MDINT Bank 64 IO_T1U AN16
MDC Bank 64 IO_L13N AM17
MDIO Bank 64 IO_L10P AP19
Table 5
ETH1 Interface to FPGA pin mapping
Interface Signal FPGA Bank FPGA Signal FPGA pin
ETH1 TXD0 Bank 64 IO_L6N AU19
TXD1 Bank 64 IO_L4P AV19
TXD2 Bank 64 IO_L5P AT18
TXD3 Bank 64 IO_L6P AT19
RXD0 Bank 64 IO_L3P AU17
RXD1 Bank 64 IO_L5N AT17
RXD2 Bank 64 IO_L3N AU16
RXD3 Bank 64 IO_L7N AR17
TXCLK Bank 64 IO_L11P AN18
TX_CTL Bank 64 IO_L4N AW18
RXCLK Bank 64 IO_L13P AL17
RX_CTL Bank 64 IO_L7P AR18
MDINT Bank 64 IO_L8P AR20
MDC Bank 64 IO_T0U AU20
MDIO Bank 64 IO_L8N AT20
4.6.3
PPS
Two SMA connectors are provided on the front panel for user use and expected to be used for PPS
inputs or outputs.
No detailed specification for the type or levels for these signals has been given.
These are therefore connected directly to the FPGA as LVTTL/LVCMOS33 signals, and care should
be taken to ensure the allowable input voltage is not exceeded.
The interface signal to FPGA pin correspondence is listed in Table 6 .
Table 6
PPS Interface to FPGA pin mapping