Document type:
Title:
Revision date:
Revision:
User's Manual (MUT)
Mod. V895 16 Channel Leading Edge Discriminator
19/03/09
3
NPO:
Filename:
Number of pages:
Page:
00101/97:V895x.MUTx/03 v895_rev3.doc
25
16
2.6. Characteristic of the signals
INPUTS
Channels:
Negative polarity, 50 Ohm impedance; maximum input frequency:
•
140 MHz (updating)
•
80 MHz (non updating)
DC coupling; input range: -5 mV
÷
-5 V; input offset:
±
5 mV; reflections: < 4% for 2 ns
rise time input signals.
VETO:
standard NIM logic signal, high impedance, 15 ns minimum FWHM. Leading edge
of the VETO signal must precede of at least 8 ns the leading edge of the input and
overlap completely the input signal (see Fig. 2.4).
N.B.: the VETO signal doesn’t act on TEST input
INPUT SIGNAL
THRESHOLD
T
β
T
α
VETO
time
T
α
min >8 ns
T
β
>0
T
Requirements:
T >15
ns
Fig. 2.4: Veto signal
TEST:
standard NIM logic signal, high impedance, 5 ns minimum FWHM, 30 MHz
maximum input frequency.
OUTPUTS
Outputs:
Differential ECL level on 110 Ohm impedance. Pulse width adjustment: from
5
±
1 ns to 40
±
5 ns FWHM. Outputs pulses can be programmed either in Updating or Non-
Updating mode (see § 4.5). Output pulse rise/fall time: <3 ns. INPUT-OUTPUT delay:
17.5+1.5 ns.
OR:
standard NIM logic signal on 50 Ohm; maximum output frequency: 50 MHz; 4 ns
rise/fall time.
CURRENT SUM:
high impedance with rate of -1 mA + 20% per hit; maximum output
frequency: 25 MHz; 8 ns rise/fall time.
MAJORITY:
standard NIM logic signal on 50 Ohm.