27/09/2002
V560 User Manual
21
4.8. COUNTERS
(Base a %10 ... Base a % 4C read only)
There are sixteen 32 bit read only registers. They contain the 32 bit value of the corresponding
counting channels
These registers can be read in D16/D32 mode. When the D16 mode is used (word cycles), the
register content is located on the 16 bit data bus following Motorola standard, i.e., the most significant
word is located at the lowest VME address. The Figs 4.3 and 4.4 show how the counter value is
located on the data bus in the two different cases.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS
Base + % 10
Base + % 14
Base + % 18
C o u n t e r 0 < 31 . . 0 >
C o u n t e r 1 < 31 . . 0 >
C o u n t e r 2 < 31 . . 0 >
Fig. 4.4: Counter value disposition on the data lines
during Long Word read cycles.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS
Base + % 10
Base + % 12
Base + % 14
C o u n t e r 0 <31..16>
Base + % 16
Base + % 18
Base + % 1A
C o u n t e r 0 <15..0>
C o u n t e r 1 <31..16>
C o u n t e r 1 <15..0>
C o u n t e r 2 <31..16>
C o u n t e r 2 <15..0>
Fig. 4.5: Counter value disposition on the data lines
during Word read cycles.
The status of the VETO is latched whenever a counting channel is read via VME; and it is available in
the Interrupt Level & VETO register (8th bit):
•
VETO = 0 the module was in the inhibit state when the channel has been read;
•
VETO = 1 the module was able to count when the channel has been read.
If the module was able to count, the counter value previously read has been latched "on fly" and may
be not correct.
During word cycle the VETO value is latched during the access at the lowest addresses.
During word cycle the 32 bit counter value is latched during the access at the lowest addresses.
