CAEN
Electronic Instrumentation
UM5175
–
V2495/VX2495 User Manual rev. 1
48
10.5
Porting V1495 to V2495
Firmware designs targeted to the V1495 User FPGA can be ported to V2495 by keeping in mind the following
differences between the two modules:
-
The V2495 FPGA device is different (Cyclone V versus Cyclone I) and with larger logic resources. While there will
be no resource constrains, the FPGA configuration scheme and output binary files are different for the two
boards.
-
A design that used on-board delay lines with V1495 must be redesigned to take into account the new features and
characteristics of the V2495 GDG.
-
The address map of the V1495 VME FPGA and V2495 MAIN FPGA have some differences to take into account:
o
Registers in V1495 are mapped at 16-bit aligned addresses, while V2495 features a 32-bit aligned address
map. Access in VME D16 mode is still possible with V2495, but discouraged. Register access should always
be in D32 mode.
o
Common registers with different address:
▪
VME Interrupt level register:
•
0x8004 in V1495
•
0x8008 in V2495
▪
VME Interrupt Status/ID register:
•
0x8006 in V1495
•
0x800C in V2495
▪
GEO address register:
•
0x8008 in V1495
•
0x8010 in V2495
▪
Firmware revision:
•
0x800C in V1495
•
0x8200 in V2495
-
The local bus map is the same for V1495 and V2495. Block transfers are allowed only in the 0x0000-0x0FFF
address interval. The same user data prefetch mechanism is implemented. Local bus register accesses are mapped
to the same 0x1000-0x7FFF address interval.
Note:
The V2495 no longer requires the 0x100C local bus address to be reserved for user firmware revision register
with special constraints due to the firmware licensing mechanism. In V2495 all user register can be implemented in the
allowed address range without any constraints of functionality or content
-
The flash access register map and protocol is different between the two boards: the specific setting and tools
must be used for each module.
