PMCDIO64
Copyright
2000 BVM Ltd.
13
7. Programming
7.1
PCI Configuration Details
A pre-programmed EEPROM contains the BVM PCI Vendor ID, which is 15C0 (hexadecimal) and the
PCI Device ID, which is 02FF (hexadecimal) and the BVM PCI Subsystem Vendor ID, which is 15C0
(hexadecimal) and the PCI Subsystem Device ID, which is 0265 (hexadecimal).
7.2 Address
Map
The PMCDIO64 uses BAR2 for access to the user accessible registers which are mapped into PCI
memory space as shown below. BAR0 is used for access to the PCI9030 configuration register offsets
which are also mapped into PCI memory space. Details of PCI9030 configuration are not covered in
this User's Manual - see section "A.1 PCI9030 PCI Interface (on page 17)" for further details. BAR1,
BAR3 and above are unused.
Address
Description
Access
Size
007 - 000
Input Register
R
64
00f - 008
Output Register
R/W
64
017 - 010
Change Flags Register
R
64
018
Direction Register
R/W
8
019
Function Register
R
8
01B - 01A
Status & Control Register
R/W
16
0FF - 01C
Reserved (reads 0)
R
100
Watchdog Trigger Register
R/W
8
103 - 101
Unused (undefined)
104
Watchdog Timer Register
R/W
8
107 - 105
Unused (undefined)
108
Watchdog Status Register
R
8
1FF - 109
Unused (undefined)
7.3 Register
Descriptions
7.3.1 Input
Register
The 64-bit read only Input Register contains a latched version of the I/O pins on the logic device. The
signal is latched by the 33MHz PCI clock. When reading back the output signals, no account is taken
of values beyond the I/O buffers. To read a 64-bit register requires two 32-bit PCI read cycles, each of
which generates two 16-bit read cycles on the local bus. As data consistency across the register
cannot be guaranteed, an "input lock bit" is provided in the Status & Control Register - see section
"7.3.6.5 Input Lock (Bit 12: INLOCK) (on page 14)" - when this bit is set the input buffer will not update.
7.3.2 Output
Register
The 64-bit read/write Output Register contents are output to valid output pins. To write to a 64-bit
register requires two 32-bit PCI writes, each requiring two 16-bit write cycles on the local bus. This
means that it is impossible to ensure that all outputs are updated at the same time. For this reason an
"output hold bit" is provided in the Status & Control Register - see section "7.3.6.6 Output Hold (Bit 13:
OUTHLD) (on page 14)" - when this bit is set the contents of the output buffer can be altered without
affecting the outputs, when this bit is cleared all outputs will change to their new value at the same
time.
7.3.3
Change Flags Register
The 64-bit read only Change Flags Register contains bits which indicate whether that particular input
caused a change-of-state to occur. The change-of-state function is enabled in the Status & Control
Register - see section "7.3.6.7 Interrupt On Change-of-State Enable (Bit 14: IOCEN) (on page 14)".
The overall status of the change-of-state can be determined in the Status & Control Register where
the Change Flags can also be cleared - see section "7.3.6.8 Interrupt On Change-of-State Status (Bit
15: IOCST) (on page 14)".
