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BVME4000/6000
Copyright
1993,1995,1998,2001 BVM Ltd.
3.10 VMEbus
Interface
Full VMEbus system controller functions are provided including SYSCLK drive, Bus time out monitor,
SYSRESET drive and an efficient 4 level bus arbiter working in prioritised (PRI), single level (SGL), or
round robin (RRS) arbitration modes.
3.10.1 VMEbus
Master
Byte or Word Master accesses may be made to the Standard (A24) and Short I/O (A16) address
spaces, Byte, Word and Longword Master accesses may be made to the Extended (A32) address
space. BVME4000/6000 Longword accesses to the A24 or A16 address space may be converted to
two Word cycles, or proceed as a Longword cycle dependant upon the BVME4000/6000 address
space accessed. Read Modify Write (RMW) cycles are supported for all of these accesses.
VMEbus arbitration is normally configured to be Release On Request (ROR) method. This may be
changed to Release When Done (RWD) with a PLD change. Both schemes use FAIR requesting,
ensuring each master has an equal chance of obtaining the bus. Digital bus busy filtering and
arbitration interleaving is used to ensure premium arbitration performance.
3.10.2 VMEbus
Slave
The memory module and on-board SRAM are dual ported onto the VMEbus. The VMEbus base
address, size of window and local base address are programmable for the A24 and A32 address
spaces. The BVME4000/6000 responds to Byte and Word and Longword Slave accesses to the A32,
A24 and A16 address spaces.
The BVME4000/6000 can snoop VMEbus slave accesses if enabled to do so. Thus although the CPU
uses extensive caching, full coherency is maintained by the CPU providing any data that is 'stale' in
the accessed memory - refer to "Appendix B CPU Cache Coherency and Bus Snooping (on page 62)".
A VMEbus location monitor is also supported in the A16 address space. This is a fixed 256byte
window size, and the VMEbus base address is programmable. A local interrupt can be enabled when
the A16 VMEbus window is accessed.
The BVME4000/6000 is compatible with VMEbus address pipelining and RMW cycles.
