Broadcom NetXtreme/NetLink BCM5717 Programmer'S Manual Download Page 493

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Non-Volatile Memory (NVM) Interface Registers

BCM5718 Programmer’s Guide

Broadcom

January 29, 2016 • 5718-PG108-R

Page 493

NVM Access Register (offset: 0x7024)

NVM Write1 Register (offset: 0x7028)

Name

Bits

Access

Default
Value

Description

Reserved

31:5

–

Disable Auto EEPROM reset

1'b0

This bit controls the nvm state machine to issue

EEPROM reset.
1'b0: Issue EEROM reset sequence before any

EPROM RW access right after a hardware or

software reset.
1'b1: EEPROM reset sequence is not issued

automatically.

EPROM SDA_OE mode

1'b1

This bit controls EPROM SDA_OE generation.

Ate_mode

When 1, the EEPROM Data in and data out are

on 2 different pins so that we don't need to worry

about the turnaround issues.

NVM Access Write Enable

When 1, allows the NVRAM write command to be

issued even if the NVRAM write enable bit21 of

the mode control register 0x6800.

NVM Access Enable

When 0, prevents write access to all other

NVRAM registers, except for the Software

arbitration register.

Name

Bits

Access

Default
Value

Description

Reserved 31-16

–

Write Disable Command

15-8

0x4h

Flash write disable command when device with

protection function is used. This command will be

issued by the flash interface state machine

through SPI interface.
To flash device, and make the flash device write-

disabled.

Write Enable Command

7-0

0x6h

Flash write enable command when device with

protection function is used. This command will be

issued by the flash interface state machine

through SPI interface.
To flash device, and make the flash device write-

enabled.
Arbitration Watchdog Timer Register (offset:

0x702C).

Summary of Contents for NetXtreme/NetLink BCM5717

Page 1: ...5718 PG108 R 5300 California Avenue Irvine CA 92617 Phone 949 926 5000 Fax 949 926 5203 January 29 2016 Programmer sGuide BCM5718 NetXtreme NetLink BCM5718 Family Programmer s Guide...

Page 2: ...Setup on page 90 RCB Setup Pseudo Code on page 91 Summary of Register Settings to Support Jumbo Frames on page 129 Receive MTU Size Register offset 0x43C on page 316 BM Hardware Diagnostic 2 Register...

Page 3: ...e 152 RX TIME STAMP LSB REG Offset 0X06B0 on page 163 RX TIME STAMP MSB REG Offset 0x06B4 on page 163 RX PTP SEQUENCE ID REG Offset 0X06B8 on page 163 RX LOCK TIMER LSB REG Offset 0x06C0 on page 164 R...

Page 4: ...ata and Receive BD Initiator Mode Register offset 0x2400 on page 341 Link Speed 10 MB No Link Power Mode Clock Policy Register offset 0x3604 on page 356 Link Speed 100 MB Power Mode Clock Policy Regis...

Page 5: ...page 462 Write DMA Mode Register offset 0x4C00 on page 464 Low Priority Mailboxes on page 469 Interrupt Mailbox 0 Register offset 0x5800 on page 469 Other Interrupt Mailbox Register offset 0x5808 0x58...

Page 6: ...Negotiation 10 100 1000 Speed with Half and Full Duplex Support on page 206 MSI X Capabilities Registers on page 281 PCIe Capabilities Registers on page 282 VRQ Flush Control Register Offset 0x2410 o...

Page 7: ...538 Added Clause 45 register Dev3 Reg803Eh read Procedure to Clause 45 Register Dev 3 Reg14h 20d EEE Capability Register on page 601 NIC Ring Addresses information to Memory map tables in Appendix C...

Page 8: ...Added HTX2B Perfect Match 1 4 HI Reg offset 0x4880 0x4888 0x4890 0x4898 on page 330 HTX2B Perfect Match 1 4 LO Reg offset 0x4884 0x488C 0x4894 0x489C on page 330 HTX2B Protocol Filter Reg offset 0x6D0...

Page 9: ...ed Host Ring Size to Table 7 Receive Return Rings on page 70 Corrected typo in Figure 26 Send Driver Interface on page 119 Corrected typo in Figure 27 Receive Producer Interface on page 120 Corrected...

Page 10: ...set 0x4800 on page 398 LSO Read DMA Corruption Enable Control Register offset 0x4910 on page 413 Added BCM5719 to Write DMA Mode Register offset 0x4C00 on page 443 Added BCM5719 to MSI Mode Register o...

Page 11: ...g Register for TCP Segmentation offset 0xCEC on page 321 Jumbo Producer Ring NIC Address Register offset 0x244C on page 337 Receive Producer Length Flags Register offset 0x2458 on page 337 Receive Pro...

Page 12: ...Programming the Ethernet Controllers 50 Section 2 Hardware Architecture 51 Theory of Operation 51 Overview of Features 52 Receive Data Path 54 RX Engine 54 RX FIFO 54 Rules Checker 55 RX List Initiato...

Page 13: ...and Consumer Indices 70 Ring Control Blocks 71 Send Ring Control Blocks 71 Receive Ring Control Blocks 72 Send Rings 73 Send Buffer Descriptors 75 Standard Not Large Segment Offload 75 Large Segment...

Page 14: ...Registers and Status Block 94 Host Buffer Allocation 94 Receive Rules Setup and Frame Classification 95 Receive Rules Configuration Register 95 Receive List Placement Rules Array 96 Class of Service E...

Page 15: ...eturn Ring s 122 Send Buffer Descriptor 122 Status Block 124 Misc BD Memory 125 Device Driver Interface 125 Send Interface 125 Receive Interface 126 Large Segment Offload LSO TSO 128 Summary of Regist...

Page 16: ...Offset 0x6900 160 EAV REF COUNT CAPTURE MSB REG Offset 0x6904 160 EAV REF CLOCK CONTROL REG Offset 0x6908 161 EAV REF COUNT SNAP SHOT LSB 0 REG Offset 0X6910 162 EAV REF COUNT SNAP SHOT MSB 0 REG Off...

Page 17: ...State Register 184 PCI Base Address Register 184 Bus Interface 186 Description 186 Operational Characteristics 187 Read Write DMA Engines 187 Expansion ROM 187 Description 187 Operational Characterist...

Page 18: ...rame Data 1 and Byte Swap Non Frame Data 1 202 Section 10 Ethernet Link Configuration 203 Overview 203 GMII MII 203 Configuring the Ethernet Controller for GMII and MII Modes 203 Link Status Change In...

Page 19: ...r Interrupt Processing Flow 232 Flowchart for Servicing an Interrupt 232 Interrupt Procedure 233 Host Coalescing 234 Description 234 Operational Characteristics 234 Registers 235 MSI 236 Traditional I...

Page 20: ...68 9 258 Clear Interrupt Mask Interrupt Mask Mode 0x68 0 0x68 1 0x68 8 259 Clear Ticks On Rx Bd Events Mode 0x3c00 9 259 No Interrupt On Force Update 0x3c00 11 259 No Interrupt On DMAD Force 0x3c00 12...

Page 21: ...ter offset 0x34 277 Interrupt Register offset 0x3C 278 INT Mailbox Register offset 0x40 0x44 278 Power Management Capability Register offset 0x48 279 Power Management Control Status Register offset 0x...

Page 22: ...correctable Error Status Register offset 0x104 301 Uncorrectable Error Mask Register offset 0x108 302 Uncorrectable Error Severity Register offset 0x10C 303 Correctable Error Status Register offset 0x...

Page 23: ...esses 1 Low Register offset 0x41C 315 EMAC MAC Addresses 2 High Register offset 0x420 315 EMAC MAC Addresses 2 Low Register offset 0x424 315 EMAC MAC Addresses 3 High Register offset 0x428 315 EMAC MA...

Page 24: ...s 0x6D4 331 RSS Registers 331 Indirection Table Register 0 offset 0x630 331 Indirection Table Register 2 offset 0x634 331 Indirection Table Register 3 offset 0x638 332 Indirection Table Register 4 off...

Page 25: ...tics Registers 340 HTX2B Statistics 341 B2HRX Statistics 341 Receive MAC Static Counters 341 ifHCInOctets offset 0x880 341 ifHCINOctets_bad offset 0x884 341 etherStatsFragments offset 0x888 341 ifHCIn...

Page 26: ...ing Selector Status Register offset 0x1404 351 Send BD Ring Selector Hardware Diagnostics Register offset 0x1408 351 Send BD Ring Selector Local NIC Send BD Consumer Index Register offset 0x1440 0x147...

Page 27: ...Ring Initiator Local NIC Standard Receive BD Consumer Index offset 0x2474 368 Receive Data and Receive BD Initiator Hardware Diagnostic Register offset 0x24C0 368 B2HRX Byte count Statistics Count off...

Page 28: ...offset 0x3610 381 D0u Clock Policy Register offset 0x3614 382 Link Idle Power Mode Clock Policy Register offset 0x3618 382 APE CLK Policy Register offset 0x361C 383 APE Sleep State Clock Policy Regist...

Page 29: ...0x3C04 414 Receive Coalescing Ticks Register offset 0x3C08 414 Send Coalescing Ticks Register offset 0x3C0C 415 Receive Max Coalesced BD Count Register offset 0x3C10 416 Send Max Coalesced BD Count Re...

Page 30: ...ffset 0x4454 431 Receive Flow Threshold Register offset 0x4458 432 RDMA Registers 433 LSO Read DMA Mode Register offset 0x4800 433 LSO Read DMA Status Register offset 0x4804 435 LSO Read DMA Programma...

Page 31: ...CT_MATCH 4 23 _LOW_REG Offsets 0x5694 0x569C 0x56A4 0x572C 460 Low Priority Mailboxes 460 Interrupt Mailbox 0 Register offset 0x5800 460 Other Interrupt Mailbox Register offset 0x5808 0x5818 460 Gener...

Page 32: ...Miscellaneous Control Register offset 0x6890 477 Fast Boot Program Counter Register offset 0x6894 477 Power Management Debug Register offset 0x68A4 478 5755ME Miscellaneous Control Register offset 0x...

Page 33: ...ddressing 495 Register Field Access Type 496 Transceiver Register Map 496 00h 0Fh 10 100 1000T Register Map Detailed Description 500 00h MII_Control_Register 500 01h MII_Status_Register 501 02h PHY_Id...

Page 34: ...04h 526 1Ch Spare Control 3 Register Shadow Register Selector 05h 527 1Ch TDR Control 1 Register Shadow Register Selector 06h 528 1Ch TDR Control 2 Register Shadow Register Selector 07h 528 1Ch LED S...

Page 35: ...X1 568 ANALOG_RX2 569 ANALOG_PLL 569 GE_PRBS_CONTROL 570 GE_PRBS_STATUS 570 Clause 45 Registers 571 Clause 45 Register Dev 3 Reg14h 20d EEE Capability Register 571 Clause 45 Register Dev 7 Reg3ch 60d...

Page 36: ...577 Switch Flow Control 577 File Transfer Complete 578 Pause Control Frame 578 Appendix B Terminology 579 Appendix C Device Register and Memory Map 580 BCM5717 BCM5718 Memory Map 580 BCM5717 BCM5718 R...

Page 37: ...Receive Producer Ring RCB Setup 91 Figure 16 Class of Service Example 98 Figure 17 Overview Diagram of RX Flow 100 Figure 18 RSS Receive Processing Sequence 102 Figure 19 Relationships Between All Co...

Page 38: ...gram 213 Figure 47 Comparing Ethernet Frames Against Available Patterns 10 100 Ethernet WOL 216 Figure 48 Unused Rows and Rules Must Be Initialized with Zeros 217 Figure 49 Basic Driver Interrupt Serv...

Page 39: ...Tx RSS Mode 84 Table 16 Status Block 0 Format MSI X Multivector RSS Mode 85 Table 17 Status Blocks 1 thru 4 Formats MSI X Multivector RSS Mode 85 Table 18 Status Block Host Addresses and INT MailBox A...

Page 40: ...View 180 Table 49 GPIO Usage for Power Management for Broadcom Drivers 191 Table 50 Ethernet Controller Power Pins 191 Table 51 Endian Example 193 Table 52 Storage of Big Endian Data 193 Table 53 Stor...

Page 41: ...stic Block 225 Table 87 Integrated MAC Flow Control Registers 226 Table 88 NetXtreme Legacy Status Block Format 229 Table 89 Interrupt Related Registers 235 Table 90 MSI X Vector Mode Selection 241 Ta...

Page 42: ...0x5728 460 Table 118 VRQ_PERFECT_MATCH 4 23 _LOW_REG Offsets 0x5694 0x569C 0x56A4 0x572C 460 Table 119 BCM5717 495 Table 120 BCM5718 495 Table 121 BCM5719 495 Table 122 BCM5720 495 Table 123 02h PHY_I...

Page 43: ...r Dev 3 Reg14h EEE Capability Register 572 Table 153 Clause 45 Register Dev 7 Reg3Ch EEE Advertisement Register 572 Table 154 Clause 45 Register Dev 7 Reg803Eh EEE Resolution Status 572 Table 155 Clau...

Page 44: ...iations In most cases acronyms and abbreviations are defined on first use For a comprehensive list of acronyms and other terms used in Broadcom documents go to http www broadcom com press glossary php...

Page 45: ...s Guide Programming details for the BCM5700 BCM5701 BCM5702 BCM5703 BCM5704 BCM5705 BCM5721 BCM5751 BCM5752 BCM5714 BCM5715 and BCM57XX devices 57XX PG1XX R Broadcom CSP 2 x2 PCI Express Dual Port Gi...

Page 46: ...tes through its customer support portal https support broadcom com For a CSP account contact your Sales or Engineering support representative In addition Broadcom provides other product support throug...

Page 47: ...Dual Port Copper BCM5718 Dual Port Copper SerDes BCM5719 Quad Port Copper SerDes BCM5720 Dual Port Copper SerDes Data Management VLAN tag support IEEE 802 1Q Yes Yes Yes Yes Layer 2 priority encoding...

Page 48: ...aces PCIe 2 0 x2 Yes Yes Yes Yes PCIe 2 1 x4 No No Yes No LAN Interfaces Integrated 10 100 1000 transceiver Yes Yes Yes Yes Internal MII GMII Interface Yes Yes Yes Yes Other Bus Interfaces NC SI versi...

Page 49: ...re monitor No No Yes Yes Integrated Trusted Platform Module TPM Security Engine No No No No Process voltage 1 2V 1 2V 1 2V 1 2V CMOS linewidth 65 nm 65 nm 65 nm 65 nm Table 3 Family Revision Levels Fa...

Page 50: ...for writing your own driver The programming model for the NetXtreme NetLink Ethernet controllers does not depend on OS or processor instruction sets Programmers using Motorola 68000 Intel x86 or DEC...

Page 51: ...of QOS rules and then categorized When a packet is transmitted the TX MAC moves data from device internal memory to the PHY Both flows operate independently of each other in full duplex mode An on ch...

Page 52: ...ce can be made by an Auto Detect feature or by explicit software programming The software driver for this device is capable of loading or unloading each network port independently The DMA EMAC associa...

Page 53: ...ddition to IEEE 802 3 standard size Ethernet frames the BCM5718 family also supports jumbo frames of sizes up to 9622 bytes The BCM5718 family of controllers replaces the traditional PNP based linear...

Page 54: ...and checks it for rules matches Performs the offloaded checksum calculations RX FIFO The RX FIFO provides elasticity while data is read from PHY transceiver and written into internal memory There are...

Page 55: ...der Start Pointer Data Start Pointer RX List Initiator The RX List Initiator function activates whenever the receive producer index for any of receive buffer descriptor BD rings is written This value...

Page 56: ...IC internal memory into TX FIFO Moving data from TX FIFO to PHY Checksum substitutions not calculation Updating statistics TX FIFO The TX FIFO provides elasticity while data is moved from device inter...

Page 57: ...st internal memory The PCI read FIFO provides a small buffer for the data read from host memory while the Read DMA engine requests internal memory via the memory arbiter The data is moved out of the r...

Page 58: ...data to the host memory from the write FIFO Performs byte and word swapping Interrupts the host using a line or message signaled interrupt Write FIFO The write FIFO provides elasticity during data mo...

Page 59: ...vice system performance LED Control Refer to section LED Control in the applicable data sheet Memory Arbiter The Memory Arbiter MA is a gatekeeper for internal memory access The MA is responsible for...

Page 60: ...r a Message Signaled Interrupt MSI Although update criteria are calculated separately all updates occur at once This is because all of the ring indices are in one status block and any host update upda...

Page 61: ...r see Send Coalescing Ticks Register Offset 0x3c0c on page 254 The send coalescing timer has expired and new frames have been consumed from any send ring and a host update has not occurred The send co...

Page 62: ...rossover so that each transceiver s transmitter is connected to the other receiver The Ethernet controllers can perform an automatic MDI crossover when the Disable Automatic MDI Crossover bit in the P...

Page 63: ...D 4 MII_TXCLK TX_ER TX_EN Media Status I O COL CRS LNKRDY RX Media Access Mgmnt RX MAC Rx Data Decapsulation TX Media Access Mgmnt TX MAC Tx Data Encapsulation MAC Sublayer Physical Layer RX I O Symbo...

Page 64: ...T 3 uses three encoding levels 1 0 and 1 Both physical signaling protocols are transparent to the MAC sublayer and are digitized by the PHY The PHY encodes decodes analog waveforms at its lower edge w...

Page 65: ...E 802 3ab specification shows the data bit to symbol mapping The code group representation is also referred to as a quartet of quinary symbols TA TB TC TD The modulation rate on the wire is measured a...

Page 66: ...to the MAC using MDIO Management Data Interrupt The integrated Broadcom PHY may be programmed to generate interrupts A PHY status change initiates a Management Data Interrupt MDINT A MDI mask register...

Page 67: ...xternal NVRAM for the purpose of housing OEM programmable configuration items refer to Application Note NetXtreme AN60x R NetXtreme NetLink NVRAM Configuration Options Refer to Broadcom Application No...

Page 68: ...small low cost external NVRAM device that contains only a very condensed amount of configuration information along with any small boot code patches that may be necessary to optimize the functionality...

Page 69: ...ommunicate information back and forth Each ring is composed of an array of buffer descriptors that reside in host memory These buffer descriptors point to either send or receive packet data buffers Th...

Page 70: ...sumer Indices mark which descriptors are currently valid in the ring see Figure 11 When the Producer and Consumer Index are equal the ring is empty When the producer is one behind the consumer the rin...

Page 71: ...icates the number elements in the ring The valid values for this field are 32 64 128 256 512 1024 2048 and 4096 Max ring sizes supported in the BCM5718 Family are shown below Rx Return 4096 Rx Produce...

Page 72: ...1C 3 4 5 IOV Mode Only 16 Host Address High 0x1F0 Host Address Low 0x1F4 Max Length Flag 0x1F8 NIC Address 0x1FC These are Memory Mapped registers Note Address range 0x100 0x10F is the legacy single R...

Page 73: ...ost Address Low 0x2534 0x2524 0x224 Max Length Flag 0x2538 0x2528 0x228 NIC Address 0x253C 0x252C 0x22C 3 Host Address High 0x2550 0x2540 0x230 Host Address Low 0x2554 0x2544 0x234 Max Length Flag 0x2...

Page 74: ...the TX RX coalescing timers expire or when the RX TX max coalesced frames thresholds are met Software can examine the TX consumer indices in the status block to determine which packets have been sent...

Page 75: ...s bit should only be set in the descriptor that points to the buffer containing the IPv4 header It is assumed that the IPv4 header is contained in a single buffer 2 PACKET_END If set to 1 the packet e...

Page 76: ...ne Normally this bit should be set to 0 9 CPU_POST_DMAa If set to 1 the controller s internal CPU is required to act upon the packet before the packet is given to the internal Send Data Completion sta...

Page 77: ...n the host software driver has a free host receive packet buffer available for incoming packets it will fill out a receive buffer descriptor and have that descriptor point to the available buffer Host...

Page 78: ...return ring producer index in status block will be used by host software in determining whether new packets have been received Receive Buffer Descriptors The format of Standard Receive Buffer Descript...

Page 79: ...1 by the controller if the controller calculated that the TCP or UDP checksum in the corresponding incoming packet was correct 12 IP_CHECKSUM In producer rings this bit should be set to 0 In return ri...

Page 80: ...incoming packet that had an IEEE 802 1Q and IEEE 802 3ac compliant header Error_Flags Contains bits flags that contain error information about an incoming packet that the descriptor is associated with...

Page 81: ...r Rx Return Ring number 0 rather than in a register See Appendix C Device Register and Memory Map on page 580 for more information A Ring Control Block RCB consists of four 32 bit words host address h...

Page 82: ...system The Status Block contains some of the Producer and Consumer indices for the rings described in Descriptor Rings on page 69 These Producer and Consumer indices allow host software to know what...

Page 83: ...Format single vector RSS Bit 0 Update bit Bit 1 Link status change Bit 2 Error attention Bits 31 3 Reserved 0x0 Table 14 Status Block Format MSI X Single Vector or INTx RSS Mode Offset 31 1 6 15 0 0x0...

Page 84: ...t 0 Update bit Bit 1 Link status change Bit 2 Error attention Bits 31 3 Reserved always 0x0 Table 15 Status Block Format MSI X Single Vector or INTx RSS Mode Offset 31 1 6 15 0 0x00 Status Word 0x04 3...

Page 85: ...0 0x00 Status Word 0x04 31 8 Reserved 0x0 7 0 Status Tag 0x08 Receive Standard Producer Ring Consumer Index Reserved 0x0 0x0C Reserved 0x0 Reserved 0x0 0x10 Send BD Consumer Index Reserved 0x0 0x14 Re...

Page 86: ...8 0x200 Link Status change Error Attention SBD Ring 1 Cons Index Std RBD Cons Index Jmb RBD Cons Index Used in all MSI X modes for Vector 0 1 0x3D00 0x3D04 0x208 Rx Return Ring 0 Prod Index Used only...

Page 87: ...ing Receive Return ring When a Producer Index is incremented it is a signal to software that a newly arrived receive packet is ready to be processed Send Ring Consumer Index Contains controller s curr...

Page 88: ...block and generate a line interrupt or MSI see Host Coalescing on page 234 for further details regarding interrupts when a specified host coalescence criteria is met Once the interrupt is generated th...

Page 89: ...cle RX Return Ring 1 RX Return Ring 2 RX Return Ring 3 RX Return Ring 4 DMA Read Engine Local Memory List Initiator DMA Write Engine Interrupt Service Routine RX Indicate Available Rx MAC RX Return Pa...

Page 90: ...nish Threshold register the Receive MTU register and the Accept Oversized bit bit 5 in the Receive MAC Mode register Receive BD Producer Ring Replenish Threshold registers Standard Receive BD Producer...

Page 91: ...e Receive MTU Size register see Receive MTU Size Register offset 0x43C on page 316 specifies the largest packet accepted by the RX MAC packets larger than the Receive MTU are marked oversized and are...

Page 92: ...by the host software in the Host Coalescing Control registers 0x3c38 Among other status the status block displays the last 16 bit value BD index that was DMAed to the Ethernet controller from receive...

Page 93: ...ngs Return rings are the exact opposite of producer rings except that they are not categorized by the maximum length receive packets supported They are actually categorized by priority or class of rec...

Page 94: ...These return ring indices can then be read by the host software to determine the last BD index value of a particular ring that has information of the last received packet As the consumer of the receiv...

Page 95: ...sed on the rules When the host services the receive packet it can service the lower numbered rings first A rule can be changed by first disabling it by setting 0 into Enable bit bit 31 in Receive BD R...

Page 96: ...ster Table 23 Receive List Placement Rules Array memory offset 0x480 0x4ff Bit Name RW Description Default 31 E RW Enable Enabled if set to 1 30 RW And With Next This rule and next must both be true t...

Page 97: ...er RW Header Type specifies which header the offset is for 000 Start of Frame always valid 001 Start of IP Header if present 010 Start of TCP Header if present 011 Start of UDP Header if present 100 S...

Page 98: ...ompliant packets are automatically supported by the Ethernet controller There is no register or setting required to receive packets that are VLAN tagged The VLAN tag is automatically stripped from the...

Page 99: ...EE 802 1Q VLAN tag inserted Table 25 Frame Format with 802 1Q VLAN Tag Inserted Offset Description 0 5 MAC destination address 6 11 MAC source address 12 13 Tag Protocol ID TPID 0x8100 14 15 Tag Contr...

Page 100: ...d to the Ethernet controller from the host based Receive Producer Ring 3 The Ethernet controller updates the Receive Consumer Index in the Host Block register and stores copy of the BD 4 A valid Ether...

Page 101: ...controller as the producer then updates the receive return ring producer index in the Status Block register corresponding to one of host memory s receive return rings and DMAs the BD to that receive r...

Page 102: ...ng disabling these hash types are provided in Receive MAC Mode register at offset 0x468 Any combination of these hash types can be enabled Four tuple of source TCP Port source IP version 4 IPv4 addres...

Page 103: ...ces require a reset to change any of the hash type hash mask and hash key parameters If the hash type flags in Receive MAC Mode register offset 0x468 enable only one type of hash then any received pac...

Page 104: ...eive buffer descriptor RBD of the receive producer ring 3 Based on the derived CPU number the device DMAs the used RBDs into appropriate receive return rings in host memory 4 The device fires the inte...

Page 105: ...send rings are shared data structures that are used to describe a series of data buffers that will be transferred onto the network The shared data structure is called the Ring Control Block RCB and t...

Page 106: ...cause of this configuration the producer index always points to an empty slot Thus there will always be at least one empty slot in a ring Figure 19 illustrates the relationships between all the compon...

Page 107: ...devices support a host based send ring The Send BDs of the host based Send Ring will be bus mastered from host memory into device local memory The device driver will program the BDs directly in its me...

Page 108: ...n to the corresponding send ring host producer index mailbox register starting at offset 0x300 for host standard see Send BD Ring Host Producer Index Register offset 0x300 0x307 on page 308 which may...

Page 109: ...t it into the outgoing frame the host software must set the appropriate control bits in the send buffer descriptors associated with the frame and seed the checksum field with zero or with the pseudo h...

Page 110: ...t request and the controller can break the large TCP packet down into smaller segments of 1448 bytes add the TCP IP and data link layer protocol headers to each segment and send the resulting frames o...

Page 111: ...e Bits Access Default Value Description Hardware Pre DMA Enable 3 RW 0 Enable hardware LSO pre DMA processing Table 28 Read DMA Mode Register offset 0x4800 Name Bits Access Default Value Description H...

Page 112: ...he length of the frame or TCP large segment to be transmitted VLAN Tag 15 0 This field is the VLAN Tag to be inserted into the frame if Flags 6 is set to 1 HdrLen 7 0 This field is the length of the E...

Page 113: ...ble This bit enables calculation of TCP or UDP checksums for IPv4 and IPv6 transmitted packets The driver will set this bit only if the packet contained within a buffer is TCP or UDP over IPv4 or IPv6...

Page 114: ...e SBD may be either set or cleared The hardware still works as expected when LSO is in use i e checksums are calculated inserted by the hardware since this is a natural requirement for doing LSO 8 CPU...

Page 115: ...ion Enable bit 31 in the Buffer Manager Mode register 0x4400 Do not set bit 5 Multiple Segment Enable in 0xC00 Send Data Initiator Mode register Example TCP segmentation related LSO register values So...

Page 116: ...o and standard frames share The driver may inter mix jumbo and standard frames in the send ring without restriction The TX MBUF on chip memory has be upsized to 22K bytes The behavior of TX jumbo fram...

Page 117: ...ues must be provided with extended receive BDs To that end each VRQ is provided with a dedicated standard receive BD RBD ring and a dedicated jumbo RBD Ring Other Miscellaneous BD memory has been incr...

Page 118: ...the entire length of the data associated with the buffer descriptor which is so because the receive return ring contains only a single length field All BDs posted to the return ring by the controller...

Page 119: ...y valid if the BD_FLAGS_FRAME_HAS_ERROR bit see Table 32 on page 120 is set in the Flags field The VLAN Tag field is filled in if the BD_FLAGS_VLAN_TAG bit is set in the flags field It is the 2 byte V...

Page 120: ...nsumer index is also reported to the host via the status block See Send Buffer Descriptor on page 122 Table 32 Receive BD Flags Bit Flag Name Flag Description 0 Reserved 1 Reserved 2 BD_FLAG_END The f...

Page 121: ...same at 0x2450 0x245F The send ring RCB and return ring RCBs are memory mapped Figure 24 Ring Control Block The host ring address is the host address of the first ring element The host ring address is...

Page 122: ...Return Ring s There are no structural changes to the return rings in the BCM5718 family There are no functional changes from standard size frames or from a Receive Side Scaling RSS perspective The imp...

Page 123: ...ets 2 Packet End This bit is set for the last send buffer in a packet 3 Jumbo Frame Driver must set this bit to 1 if the MTU length of the Send Frame is 1500B The MTU length is the Ethernet payload le...

Page 124: ...d structure of the status block is shown in Table 35 below Note that there are multiple formats of status blocks 9 CPU Post DMA If this bit is set the CPU is required to act upon the buffer before the...

Page 125: ...On chip send BD cache On chip standard receive BD cache On chip jumbo receive BD cache Software gencomm area driver firmware communication shared memory area Device Driver Interface There are minimal...

Page 126: ...t Max Frame Size arrives the controller attempts to place the frame in such a buffer and ends up truncating the frame RX frames larger than Max Frame Size are placed in buffers retrieved from the RX j...

Page 127: ...ed to the controller via the receive return consumer ring index mailbox register A conceptual diagram of the Receive Return Interface is shown in Figure 28 on page 128 below Host Memory Host Buffer n...

Page 128: ...ol Block RX Return Ring 0 Note The RCB s host ring address field points to the first element of the Ring in the host Status Word Status Tag RX Std Cons 0 31 Status Block Rcv Return 1 TX Cons 1 Status...

Page 129: ...d ring size power of 2 15 2 std_max_packet_size 0x600 1522 decimal 1 0 0 0x245C Standard NIC address 0x400000 The NIC address is a controller internal memory address where the controller caches a port...

Page 130: ...r descriptors Receive BD and the Transmit MAC processes send buffer descriptors Send BD Figure 29 illustrates the relationship between a frame consisting of multiple fragments and their corresponding...

Page 131: ...simplicity the diagram depicts the operation of a single ring 1 The host software calls a system API to retrieve the three physical fragments of the frame It initializes the next three send buffer de...

Page 132: ...Figure 30 Transmit Data Flow NIC Memory Host Memory Send BD 1 Send BD 2 Send BD 3 Send BD 4 Send BD 5 Send BD 6 Send BD 7 Send BD 8 SendBD 512 Frame Buffer 1 Buffer 2 Buffer 3 Send Producer Index Buff...

Page 133: ...that a new packet is ready to be transmitted Examine packet if necessary and decide which send ring to use Is this the last virtual buffer for this packet Set BD_FLAG_END bit in send BD Make OS call...

Page 134: ...xample An NDIS driver issues a device reset via the Core Clock Blocks Reset bit see Table 358 on page 334 After the reset is completed the RX RISC begins executing the boot code as if the power was fi...

Page 135: ...on address is fed into the normal CRC algorithm in order to generate a hash function The most significant bits of the CRC are then used without any inversion in reverse order to index into a hash tabl...

Page 136: ...ght most bit bit 0 of the current remainder XORed with the data bit equal 1 then remainder remainder shifted right one bit XOR 0xEDB88320 else remainder remainder shifted right one bit 2 Invert remain...

Page 137: ...e j 6 The most significant 7 bits of the CRC32 no inversion are used to index into one of the possible 128 bit positions Bitpos Crc32 0x7f Hash register index RegIndex Bitpos 0x60 5 Bit to turn on wit...

Page 138: ...he Ethernet controller operating in promiscuous mode ignores multicast and MAC address filtering Multicast Hash Table Setup Configuration on page 135 and MAC Address Setup Configuration on page 135 bu...

Page 139: ...If the Max Payload Size of PCIe Device Control register is 128 bytes set the DMA write water mark bits bits19 21 of DMA Read Write Control register to 011b for a water mark of 128 bytes if the Max Pa...

Page 140: ...er Ring The threshold values indicate the number of buffer descriptors that must be indicated by the host software before a DMA is initiated to fetch additional receive descriptors in order to repleni...

Page 141: ...ve BD Standard Producer Ring Index mailbox see Receive BD Standard Producer Ring Index Register offset 0x5868 on page 461 23 Configure the MAC unicast address See MAC Address Setup Configuration on pa...

Page 142: ...guration Register offset 0x2010 on page 358 allows host software to initialize QOS rules checking For example a value of 0x181 as used by Broadcom drivers breaks down as follows One interrupt distribu...

Page 143: ...tatus data see Status Block Host Address Register offset 0x3C38 on page 421 This register accepts a 64 bit value in register 0x3C38 high order 32 bits and 0x3C3C low order 32 bits 39 Enable the host c...

Page 144: ...errun_Attention_Enable Write_DMA_PCI_FIFO_Underrun_Attention_Enable Write_DMA_PCI_FIFO_Overwrite_Attention_Enable Write_DMA_Local_Memory_Read_Longer_Than_DMA_Length 48 Set bit 29 of the Write DMA Mode...

Page 145: ...le bits in the Send BD Selector Mode register see Send BD Ring Selector Mode Register offset 0x1400 on page 351 63 Enable the transmit MAC by setting the Enable bit and the Enable_Bad_TxMBUF_Lockup_fi...

Page 146: ...ocessor architecture is little endian Set the Enable_Endian_Word_Swap bit and the Enable_Endian_Byte_Swap bit in the Miscellaneous Host Control register when the host processor architecture is big end...

Page 147: ...000 ms for Flash devices and 10000 ms for SEEPROM devices Device Closing Procedure This section describes the device close procedure for the MAC portion of the NetXtreme family of devices 1 Disable Ho...

Page 148: ...Call Device Reset Procedure see Device Reset Procedure on page 146 7 Instruct the firmware do the following post reset Note Do this only if ASF enabled a write 0x2 to the device memory offset 0xc04 b...

Page 149: ...write 0x0E 0x003C mii_write 0x0D 0x4007 mii_write 0x0E 0x0000 val mii_read 0x0E Disable MAC control of LPI reg_write 0x36B0 reg_read 0x36B0 0x00100000 Link status interrupt handler Check for PHY link...

Page 150: ...nitialized the following algorithm may be used to verify EEE link status i 0 while i 100 if mii_read 0x11 0x100 0x100 if mii_read 0x19 0x700 0x700 if mii_read 0xA 0x7000 0x7000 mii_read 0xA 0x3000 0x3...

Page 151: ...Energy Efficient Ethernet BCM5718 Programmer s Guide Broadcom January 29 2016 5718 PG108 R Page 151...

Page 152: ...apest and simplest set of HW hooks so that a service grade PTP profile may be enabled in the host server computer The assists that NetXtreme provides are A 64 bit Counter clocked by the 125 MHz DLL cl...

Page 153: ...o compensate its local clock by using the following equation Tslave offset t2 t1 Tdelay Assume that both nodes contain a NetXtreme Time Synch Capable NIC Table 44 on page 154 describes the roles the P...

Page 154: ...it TX Time Stamp Register A bit defined in Send BD for indication of TX Time capture Receive Time Sync hardware Programmable Receive Frame Cracker A 64 bit RX Time Stamp Register A 16 bit RX PTP Seque...

Page 155: ...c attributes of this clock The rest are programmable Time referencing Time stamping Time sampling etc all real time interfacing of the chip hardware with the AV Device Driver shall be performed in ref...

Page 156: ...every time the Corrector register is updated Therefore the accumulator s value will increase with every EAV Ref clock cycle until it overflows In the EAV Reference Clock tick in which the accumulator...

Page 157: ...8 Table 45 Send Ring SBD Flags Bit Flag Name Flag Description 0 TCP UDP Checksum Offload Enable This bit enables calculation of TCP or UDP checksums for IPv4 and IPv6 transmitted packets The driver wi...

Page 158: ...esults hardware shall decide if that particular Frame had the Host SW desirable PTP message type and only then it will transfer its acquired time stamp into the RX Time Stamp Register Along with the R...

Page 159: ...iated with this buffer descriptor has an 802 1Q VLAN tag associated with it 7 RSS_HASH_TYPE Hash type of the receive packet It indicates which hash_type was used on the receive packet if multiple hash...

Page 160: ...bit to enable Time Sync Mode Legacy 20 0 Name Bits Access Default Value Description EAV Reference Count lower half 31 3 RW UUUU LSB of the EAV Reference Count Reading this LSB latches a Count in this...

Page 161: ...O shared pool we are talking PCB Hardware design here Name Bits Access Default Value Description Reserved 31 30 RO 00 APE_GPIO 3 Mapping 29 27 RW 000 Same as below APE_GPIO 2 Mapping 26 24 RW 000 Same...

Page 162: ...e between these two reads it s time stamp capture request is ignored by hardware Stop EAV Ref Count 1 RW 0 Reset EAV Ref Count 0 W1C 0 Name Bits Access Default Value Description EAV Reference Count Sn...

Page 163: ...s LSB freezes the time stamp and is only unfrozen when the corresponding MSB is read Name Bits Access Default Value Description TX Time Stamp Upper half 31 0 RO U MSB of the TX Time Stamp Reading this...

Page 164: ...6 RO 0x0 Lock Time MSB Value 15 0 RW 0x00 This concatenated with Lock Time LSB value constitutes a 48 bit Lock Timer value Precision of the value is 1ns which equates to the precision of the EAV Refer...

Page 165: ...rticular PTP message type packet to be time stamped by hardware Write a 1 in a bit position to enable time stamping of the corresponding message type and write a 0 in a bit position to disable time st...

Page 166: ...crements to match this 63 bit value Note Setting this time value back in time will produce no toggle Name Bits Access Default Value Description Watchdog LSB Value 31 0 RW 0x0000 See TX Time Watchdog M...

Page 167: ...dcom January 29 2016 5718 PG108 R Page 167 EAV REF COUNT SNAP SHOT MSB 1 REG Offset 0X6934 Name Bits Access Default Value Description EAV Reference Count Snap shot Upper half 31 0 RO U MSB of the EAV...

Page 168: ...the device and its functionality In summary three types of PCI configuration space registers may be exposed by any particular device Required Optional capabilities Device specific Network devices imp...

Page 169: ...no I O space registers Two programmable blocks expose Ethernet controller functionality to host software The first is a register block The second is a memory block The register and memory blocks map i...

Page 170: ...Internal Memory PCI Configuration Space Shadow Priority Mailboxes 1 Registers Rx CPU Scratchpad Memory Window Reserved ROM Rsvd 0xC00004001 0xC0008000 0xC0000100 0xC00002001 0xC0010000 0xC0030000 Rsvd...

Page 171: ...vice Figure 33 Header Type Register 0xE Single function PCI devices may decode access to non implemented device functions in two ways per Section 3 2 2 3 4 of the PCI 2 2 specification A single functi...

Page 172: ...s can be used in conjunction with Standard mode PCI access Indirect mode has no interdependency on other PCI access modes and is a mode in itself Table 47 Device Specific Registers Register Cross Refe...

Page 173: ...thernet controller memory block The Register_Data register allows host software to read write from the indirection position The Register_Base_Address register can be perceived as creating a cursor poi...

Page 174: ...ce 0x00000000 BCM57XX Ethernet Controller Register Block BusX Register Data Register 0x00038000 Rx CPU ROM 0x00038800 Address may be located anywhere Not Accessible via Register Indirect Mode BCM57XX...

Page 175: ...offset Access to ranges 0x00000 0x1FFFF is allowable The Memory_Window_Data register is the read write porthole for host software using the previously positioned pointer cursor This register pair acc...

Page 176: ...76 Figure 35 Indirect Memory Access PCI Configuration Space 0x00000000 Indirect Memory Access BCM57XX Ethernet Controller Memory Block BusX DeviceY Function Z Memory Data Register 0x00020000 Address m...

Page 177: ...ocated at offset 0x5880 see Receive BD Standard Producer Ring Index Register offset 0x5868 on page 461 A update write to this register indicates that host software has consumed a RX buffer descriptor...

Page 178: ...ceY Function Z UNDI Rx BD Std Ring Producer Index Mailbox UNDI Rx BD Return Ring Consumer Index Mailbox UNDI Tx BD NIC Producer Index Mailbox Rx BD Std Ring Producer Index 0x00005BFF Not Aliased Not A...

Page 179: ...address region may be decoded The BAR registers point to the beginning of the host memory mapped regions where Ethernet controller can be accessed Figure 37 Standard Memory Mapped I O Mode Host Memory...

Page 180: ...emory indirection and the Memory_Window_Data register Figure 38 Memory Window Base Address Register Figure 39 on page 181 shows how the 32K window can float in the Ethernet controller s local memory T...

Page 181: ...2K Memory Window 32K Mem Wnd Base Addr PCI Configuration Space Window may be located anywhere Window may be located anywhere Local Memory Address Space Registers 32K Physical Memory BusX DeviceY Funct...

Page 182: ...nction Z 0x00000000 PCI Cfg Space Registers Shadow Copy High Priority Mailboxes 0x00000400 0x00000200 0x00110000 Registers Memory Window Reserved IRQ Mailbox 0 3 General Mailbox 1 8 Rx BD Return Ring...

Page 183: ...ndex Tx BD Ring 1 16 Host Producer Index Tx BD Ring 1 16 NIC Producer Index Memory 0x00008000 0x00100000 Rx BD Send Producer Index 0x00130000 0x00140000 0x00180000 0x001C0000 0x01000000 0x01FFFFFF Res...

Page 184: ...odes a 64K block of host memory PCI Base Address Register The PCI_Base_Address Register BAR specifies the location of a Ethernet controller memory mapped I O block The Ethernet controller mode configu...

Page 185: ...0 3 are ignored Host software will read zero values from bits 4 16 Figure 43 shows the BAR register and the bits returned to the OS BIOS during resource allocation Figure 43 PCI Base Address Register...

Page 186: ...DMA channel and a write DMA channel Each channel corresponds to the appropriate DMA engine see Figure 44 The configuration of the DMA engines and the PCI interface is discussed in this section Figure...

Page 187: ...ite FIFO The DMA_Write_Watermark bit field is read write and is also located in the DMA Read Write register The write watermark registers default to zero after power on reset Expansion ROM Description...

Page 188: ...t Power Management Description The Ethernet controller is compliant with the PCI v2 0 PCI v2 1 for BCM5719 power management specification The MAC is programmable to two ACPI states D0 and D3 The D0 st...

Page 189: ...state is entered after a PCI reset or device software reset The assertion of PME causes the PCI bridge to drive RST The MAC hardware blocks are not initialized in this state Example The RX engine TX...

Page 190: ...down The physical layer auto advertises 10 Mbps capability in this state and link is set to 10 Mbps half duplex or full duplex The PHY is configured for WOL mode WOL pattern filters are initialized a...

Page 191: ...vel switching consumes power mW Software should selectively disable clocking to non essential functional blocks Software must set the Enable_Clock_Control_Register bit in the Miscellaneous Host Contro...

Page 192: ...it field in the PMC register will reflect this capability Disable Device Through BIOS The Ethernet controllers can be disabled that is placed in Low Power IDDQ mode through BIOS by writing the value o...

Page 193: ...owing tables Examples of big endian platforms include SGI Irix IBM RS6000 and SUN Examples of little endian platforms include Intel x86 and DEC Alpha PCI assumes a little endian memory model PCI confi...

Page 194: ...net controller registers If 1 this register enables byte swapping of frame data when it comes across the bus Word Swap Non Frame Data bit 2 Mode Control register offset 0x6800 into the Ethernet contro...

Page 195: ...equest to address 0x08 the four bytes of data returned on the PCI bus would actually be the NIC Ring Address rather than the Max_Len and Flags fields This initially might seem counter intuitive but is...

Page 196: ...g endian systems that needed PCI data little endian translated back to big endian format The following figures show the translation of data when the Enable Endian Byte Swap bit is set Internal Byte Or...

Page 197: ...d internally in big endian format However when the data gets transferred across PCI there could be confusion about the correct byte ordering because PCI is Little Endian whereas Ethernet controller is...

Page 198: ...able 62 64 Bit PCI Bus WSD 0 BSD 1 B7 B6 B5 B4 B3 B2 B1 B0 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 D4 D3 D2 D1 S2 S1 D6 D5 S6 S5 S4 S3 IP2 IP1 T2 T1 Table 63 32 Bit PCI Bus WSD 0 BSD 1 B3 B2 B1 B...

Page 199: ...e first byte on the wire byte D1 to be placed into memory at the least significant starting address of the packet data D5 D6 S1 S2 S3 S4 S5 S6 T1 T2 IP1 IP2 Table 66 64 Bit PCI Bus WSD 1 BSD 1 B7 B6 B...

Page 200: ...ost processor memory architectures the Ethernet controller can order the data in memory in four different ways depending on the settings of the Word Swap Non Frame Data and Byte Swap Non Frame Data bi...

Page 201: ...for a physical address the host device driver would have to swap the two 32 bit words that comprise the 64 bit address that the host operating system used Word Swap Non Frame Data 0 and Byte Swap Non...

Page 202: ...Swap Non Frame Data 1 and Byte Swap Non Frame Data 1 This requires the software to use the following big endian data structure on the host Table 73 Send Buffer Descriptor Big Endian 32 bit format wit...

Page 203: ...nds to the correct interface speed 01b for MII 10b for GMII Configuring How MAC Detects Link Up Down The Ethernet controller has the ability to determine if the Ethernet link is up or down The link wi...

Page 204: ...eed duplex or to examine the results of the auto negotiation process The integrated PHY registers are accessed via a process called MDIO The integrated PHY is connected to the Ethernet controller thro...

Page 205: ...PHY register 00h Force 10Base T full duplex Write 0x1000 to PHY register 1Eh Force link required for 10Base T Set MAC register 0x400 3 2 01b Set MII Set MAC register 0x400 1 0 Force full duplex opera...

Page 206: ...00 3 2 10b Set GMII Set MAC register 0x400 1 0 Force full duplex operation PHY Configuration Auto Negotiation 10 100 1000 Speed with Half and Full Duplex Support Basic PHY pseudo code Enable 10 100 10...

Page 207: ...it 14 val16 phy_read 0x10 val16 1 14 phy_write 0x10 val16 Autonegotiation 10 100 1000 speed with half and full duplex support uint16_t gig 0 anar 0 Reset PHY Enable auto MDIX Force loopback Select pau...

Page 208: ...autoneg advertisement phy_write 0x04 00001b 0 Write forced link speed phy_write 0x00 bmcr 10Base T Full Duplex uint16_t bmcr 0 Reset PHY Enable auto MDIX Set link speed to 10Mb bmcr 0 6 1 13 Set full...

Page 209: ...r 100Base TX Full Duplex uint16_t bmcr 0 Reset PHY Enable auto MDIX Set link speed to 10Mb bmcr 0 6 1 13 Set full duplex operation bmcr 1 8 Force loopback Disable 1000Mb autoneg advertisement phy_writ...

Page 210: ...r communication with the internal transceiver registers These modes are as follows Autopolling mode Enabled by setting the Enable bit in the MAC Ethernet MI Mode register The device will poll for the...

Page 211: ...0x2 4 MII_Communication_Register Start_Busy is set to 1 5 Poll Until MII_Communication_Register Start_Busy is cleared to 0 6 MII_Communication_Register Transaction_Data contains 16 bit data of the PHY...

Page 212: ...WOL mode is a combination of PHY and MAC configurations Both the PHY and MAC must be configured correctly to enable Broadcom s WOL technology The Ethernet controller provides WOL pattern filters for 1...

Page 213: ...acket comparisons The WOL state machine will move out of an Idle state when ACPI power management is enabled The WOL state machine will clear the TX FIFO and Match register The Match register indicate...

Page 214: ...gram the WOL_Pattern_Pointer register with the actual internal memory location Rather host software must first convert the base address to a pointer value Here are example conversion from memory base...

Page 215: ...and round up to nearest integer value The Ethernet controller compares 2 bytes every three memory arbiter MA clock cycles Multiply Length 2 by three clock cycles The following are example clock cycle...

Page 216: ...C2 C3 B0 B1 B2 B3 B4 B5 C0 S1 S2 S3 C0 S4 S5 S6 C0 S7 S8 S9 Nine pattern streams for simultaneousWOL compare ACPI length field is the max pattern size 10 100 Ethernet WOL ACPI Offset Field ACPI Mbuf...

Page 217: ...total length of an entry is 192 bits Each 64 bit row contains a 16 bit control word which identifies byte enables see Table 76 The remaining 48 bits contains 2 byte rules The 2 byte rules are distribu...

Page 218: ...one s complement of the T3_MAGIC_NUM back into the T3_FIRMWARE_MAILBOX If the T3_MAGIC_NUM is present the boot code will not reset the PHY After resetting the Ethernet controller host software should...

Page 219: ...for WOL mode see Table 80 The RX CPU is not required during WOL operation so its clock can be disabled The MAC has an internal phase locked loop that clocks internal logic at 133 MHz Software must sel...

Page 220: ...Management_Control Status PME_Enable Enable PCI Power_Management_Control Status Power_State 0x03 Ethernet_MAC_Mode ACPI_Power On See above Ethernet_MAC_Mode Magic_Packet_Detection See above Table 82 I...

Page 221: ...ll_Duplex Capability bits in the 1000BASE T Control Register The link partner will now only be able to auto negotiate for 10 Mbps speed full half duplex 4 Set the Restart_Auto_Negotiation bit in the M...

Page 222: ...L Only Enable the ACPI_Power On bit in the EMAC Mode Register offset 0x400 on page 310 This bit will enable logic for D3 hot cold transitions to D0 ACPI state The MAC will also be capable of asserting...

Page 223: ...negotiation PHY Auto Advertise Operational Characteristics The Ethernet controller implements pause functionality using Xon and Xoff states The MAC will extract a pause quantum from a pause control fr...

Page 224: ...able 84 shows the pause quanta based on the Enable_Long_Pause bit setting Receive MAC The Ethernet controller receive MAC s link partner may want to inhibit frame transmission until upstream resources...

Page 225: ...disabled state of Receive_MAC_Mode_Control Flow_Enabled xonPauseFramesReceived This counter is incremented under the following conditions IEEE 802 3 MAC flow control pause frame received with valid C...

Page 226: ...er_Ability_Register does not set the Pause_Capable bit The Ethernet controller should not send pause frames to this link partner since flow control is not implemented or disabled The Ethernet controll...

Page 227: ...use 802 3ab_Table_28B 3 And Auto_Neg_Advertise_Reg Pause_Capable 802 3ab_Table_28B 3 Then The current advertised state does not match 802 3 specifications Driver_ Link__link_state LINK_STATUS_DOWN Els...

Page 228: ...w control capabilities are indeterminate software cannot use the Link_Partner_Abitity registers Driver_Flow_Capability DISABLED The current link is full duplex at 10 100 1000 wire speeds Else Full Dup...

Page 229: ...tus block into host memory In addition it has mechanisms that allow host software to control when and how often the status block is updated in host memory Since the status block updates and interrupt...

Page 230: ...t the host driver either has or will touch the status block If a during interrupt event occurs the host driver can examine the update bit later to determine if a fresh status block has been moved to h...

Page 231: ...ost Control Register offset 0x68 on page 282 is set to 1 write the saved status tag to the upper 8 bits of Interrupt Mailbox 0 and 0 to the remaining bits 23 down to 0 to indicate that the ISR is fini...

Page 232: ...d schedules a callback to handle the interrupt processing many OSes due this via a lower priority thread Allternatively the driver could directly invoke the interrupt processing code Driver writes a v...

Page 233: ...eturn Ring consumer pointer in each mailbox for new RX frames 6 Check for TX completes Loop through enabled TX Send Rings Check for difference between previous consumer index software kept and current...

Page 234: ...re since the last time the host had read the status block this is called during interrupt processing When the NIC updates the status block it will make a decision about whether to assert the interrupt...

Page 235: ...terrupt Mailbox 0 register Interrupt Mailbox 0 Register offset 0x5800 on page 460 Receive Coalescing Ticks register Receive Coalescing Ticks Register offset 0x3C08 on page 414 Send Coalescing Ticks re...

Page 236: ...neration versus using a traditional interrupt are as follows Eliminates the need for interrupt signal trace on the PCI device Eliminates the need to perform a dummy read from the device by the device...

Page 237: ...beginning of the interrupt service routine The dummy read has to traverse the same bridge that memory writes from the Ethernet controller have to traverse to get to the host memory The ordering rules...

Page 238: ...rrives at the PCI host bridge the status block has already been posted to the host memory Upon receipt of the MSI message write the PCI host bridge generates the interrupt request to the processor Int...

Page 239: ...ler provides a way for firmware executed by RX RISC to generate MSI messages Firmware can generate MSI messages by using MSI_FIFO_Access register Offset 0x6008 For example if firmware wants to generat...

Page 240: ...y to map packet indication and completions into 17 MSI X vectors The MSI X specification allows a device to advertise the availability of a chosen number of vectors in its PCIe capabilities list howev...

Page 241: ...ue mode settings All permissible combinations are shown in the table below Vector allocation in each mode is shown below Single Vector Mode RSS mode Vector 0 Aggregate of the following Rx Return Ring...

Page 242: ...Vector 3 RSS Return Ring 2 Indication TXQ 3 Completion in Multi TXQ mode Vector 4 RSS Return Ring 3 Indication TXQ 4 Completion in Multi TXQ mode IOV 17 Vector mode Vector allocation would be as foll...

Page 243: ...l four receive queue indications and all four Send Completions are thus grouped together in Vector 0 While in IOV mode all 17 Rx queues and all 16 Tx queues are grouped into Vector 0 Also this mode mu...

Page 244: ...umer Indices are indicated in the legacy Status Block When MSI X Multivector RSS mode is enabled it leads to logically five interrupt vectors Each of these vectors is bound to its own status block thu...

Page 245: ...D1 Cons Index 2 0x3D08 0x3D0C 0x210 VRQ2 RR Prod Index SBD2 Cons Index RBD 2 Cons Index 0x210 Rx Return Ring 1 Prod Index SBD2 Cons Index 3 0x3D10 0x3D14 0x218 VRQ3 RR Prod Index SBD3 Cons Index RBD 3...

Page 246: ...VRQ6 RR Prod Index SBD6 Cons Index RBD 6 Cons Index N A N A 7 0x3D30 0x3D34 0x230 VRQ7 RR Prod Index SBD7 Cons Index RBD 7 Cons Indexes N A N A N A N A 16 0x3D78 0x3D7C 0x254 VRQ16 RR Prod Index SBD16...

Page 247: ...k format MSI X Single Vector IOV Mode Offset 3116 150 0x00 Status Word 0x04 31 8 Reserved 0x0 7 0 Status Tag 0x08 Single Send BD Consumer Index IF Single Send queue ELSE 0x0 Receive Return Ring 0 Prod...

Page 248: ...numbers as shown in Table 94 Status Block 0 Status Word Format Multivector RSS Bit 0 Update Bit Bit 1 Link Status Change Bit 2 Error Attention Bit 3 Resvd always 0 Bit 4 Resvd always 0 Bit 5 Resvd alw...

Page 249: ...Status Word Valid for all Status Blocks 0x04 31 8 Reserved 0x0 7 0 Status Tag n Independent for each Status Blocks 0x08 Reserved 0x0 Receive Return Ring 1 Producer Index Valid only for Status Block2...

Page 250: ...The MSI X Capability structure is implemented inside the EP RC core It points to two structures that must be implemented inside a device the MSI X Table and a Pending Bit Array PBA There is also a Mes...

Page 251: ...d the function must set the corresponding Pending bit in the PBA When this bit is 1 and a 0 is written to it a device must schedule an interrupt vector in case one was already Pending The PBA Structur...

Page 252: ...Table 99 MSI X Table and PBA Structures in BCM5718 Family MSI X Table Entry DW3 Content 32 bit DW2 Content 32 bit DW1 Content 32 bit DW0 Content 32 bit BAR4 and BAR5 Offset N A Reserved Bits 127 17 PB...

Page 253: ...to BCM5718 family Receive Coalescing Ticks Register Offset 0x3c08 The value in this register can be used to control how often the status block is updated and how often interrupts are generated due to...

Page 254: ...illed in by the device before the device updates the status block due to a receive event Whenever the device completes the reception of a packet it fills in a receive return ring BD and then increment...

Page 255: ...r and thus the interrupt is in a masked state If this parameter triggers while in During Interrupt state the controller will DMA the latest Status Block to the host memory but the interrupt will remai...

Page 256: ...ble 100 MSI X Host Coalescing Parameters Valid HC Parameter Register Set Invokes Status Block IOV Mode Multiple TXQ Netqueue VMQ TSS IOV Mode Single TXQ VMQ RSS Mode Multiple TXQ TSS RSS Mode Single T...

Page 257: ...6 SMCBCDIR 16 16 0x3EE8 0x3EEC 0x3EF0 0x3EF4 0x3EF8 0x3EFC VRQ 16 TXQ 16 0x3EE8 0x3EF0 0x3EF8 VRQ 16 N A N A N A N A RCTR n RECEIVE COALESCING TICKS REGISTER n SCTR n SEND COALESCING TICKS REGISTER n...

Page 258: ...3 Coalesce Now When INTx or MSI Enabled 0x3C00 3 Coalesce vector 0 Now When MSI X Enabled 0x3C00 13 Coalesce vector 1 Now When MSI X Enabled and Multivector mode Enabled 0x3C00 14 Coalesce vector 2 No...

Page 259: ...register cause status block update s without the corresponding interrupt event This bit applies to all MSI X vectors and respective Status Blocks No Interrupt On DMAD Force 0x3c00 12 Enabled by setti...

Page 260: ...unces effects of IPG or short gaps among packets within a burst This feature may be enabled or disabled by a register bit The countdown preload value is also programmable When enabled in conjunction w...

Page 261: ...ects of pre allocation If it is hardware starts counting down a count value programmed by this field While the count down is in progress if another Rx packet starts to pour into the Rx MBUF the FSM go...

Page 262: ...hen the Mailbox 0 register field 23 0 is written with a zero value the tag field of the Mailbox 0 register is compared with the tag field of the last Status Block to be DMAed to the host If the tag re...

Page 263: ...ues 1 Default Queue 1 Drop Queue 17 Standard Receive Producer Rings 17 Jumbo Receive Producer Rings 17 Return Rings Per Queue synchronization with Driver RX Packet Header Data Split and copy for VMQ T...

Page 264: ...il Box region see RX Mail Box Registers for VRQ on page 458 Send Mail Box Register Changes 15 Host Send Producer Index registers have been added to the High Priority Mail Box region see Send Mail Box...

Page 265: ...IOV Mode see BD Fetch Limit Register Offset 0x2D08 on page 375 VRQ Status Register Offset 0x240C Additional bits have been added to this existing register see VRQ Status Register offset 0x240C on page...

Page 266: ...s to sort the RX traffic designated for multiple VRQs based on VRQ Filter settings RX EMAC marks each RX packet with a VRQ number after placing it into the RX MBUF Before initiating a RX packet DMATo...

Page 267: ...ilities in this regard A maximum of 16 Send Rings SBD Rings Multiple Send Rings could be enumerated only in conjunction to either IOV Mode or RSS Mode All 16 Send Rings may be enabled in conjunction o...

Page 268: ...ll continue to function in all rings without any behavior change Minimal set of per Send Queue EMAC Statistics The basic Send interface with the Device Driver remains unchanged only the number of Send...

Page 269: ...0x13FF 0x1000 0x100B 0x100C 0x13FF Send data Completion Unused SBDS 0x1400 0x17FF 0x1400 0x147F 0x1480 0x17FF SBDS Registers Unused SBDI 0x1800 0x1BFF 0x1800 0x1847 0x1848 0x1BFF Send BD Initiator Un...

Page 270: ...0 0x5CFF 0x5D00 0x5FFF Flow Through Queue Unused MSI 0x6000 0x63FF 0x6000 0x6007 0x6008 0x63FF Message Signaled Interrupt Unused CFG Port 0x6400 0x67FF 0x6400 0x67FF PCIe Core Private Registers Access...

Page 271: ...ort 28 RW2C 0x0 This bit is set when a requester receives a completion with completer abort completion status Signaled Target Abort 27 RW2C 0x0 This bit is set when a function acting as a completer te...

Page 272: ...this bit or though PCI express specific bits in DCR Stepping Control 7 RO 0x0 Does not apply to PCIE Parity Error Enable 6 RW 0x0 This bit enables the write to the Master data parity error status bit...

Page 273: ...4 and bits 19 16 from Register 68 for that purpose 0x0 for A steps 0x1 for B steps 0x2 for C steps Revision ID Metal Revision ID 3 0 FW RW Host RO ASIC Rev Input This field will be updated automatical...

Page 274: ...e and is always read as 0 Path i_cfg_func i_cfg_private Name Bits Access Default Value Description Address 31 0 RW 0 These bits set the address upper 32 bit address space These bits may be combined wi...

Page 275: ...et by HARD Reset Name Bits Access Default Value Description Address 31 4 RW 0 These bits set the address within a 32 bit address space that will be card will respond in These bits may be combined with...

Page 276: ...rogrammer s Guide Broadcom January 29 2016 5718 PG108 R Page 276 Cardbus CIS Pointer Register offset 0x28 This register is reset by Hard Reset Name Bits Access Default Value Description Cardbus CIS Po...

Page 277: ...ese bits indicate the address of the Expansion ROM area ROM Size indication 23 11 RW 0x00 These bits indicate the size of the Expansion ROM area or the address of it The boundary form RO bits to RW bi...

Page 278: ...XIMUM_LATEN CY 31 24 RO 0x00 Hardwired to zero MIN_GRANT 23 16 RO 0x00 Hardwired to zero Interrupt Pin 15 8 RO 0x01 Indicates which interrupt pin this device uses 0 no Interrupt 1 Use Interrupt A 2 Us...

Page 279: ...upports the D1 PM state This device does not support D1 Aux Current 24 22 RO FW RW 0x0 This device supports the data register for reporting Aux Current requirements so this field is N A DSI 21 RO 0x0...

Page 280: ...reset upon transitioning from D3hot to D0 via software control of the PowerState bits Configuration Context is lost when performing the soft reset Upon transition from the D3hot to the D0 state full r...

Page 281: ...ip is set to generate 16 messages 5 32 Chip is set to generate 32 messages Multiple Message Capable 19 17 RO 0x3 These bits indicate the number of messages that the chip is capable of generating This...

Page 282: ...ata 15 0 RW Unknown MSI Data Name Bits Access Default Value Description ASIC Rev ID 31 28 R Product ID input 0xF Indication that BCM5718 family follows new PRODUCT REV ID mapping 27 24 R ASIC Rev Inpu...

Page 283: ...wise the register is read only Enable Endian Word Swap 3 RW 0 Set this bit to enable endian word swapping when accessing through PCIE target interface Enable Endian Byte Swap 2 RW 0 Set this bit to en...

Page 284: ...d MRRS for slow speed 6 4 RW 0 This setting is for 10 100M Ethernet DMA read MRRS The pcie_core will accord to this value to be max DMA read length This configuration has no effect for GIGA mode 0 102...

Page 285: ...is set the APE control registers may be written Config Retry 15 RO 0x1 On Hard reset When asserted forces all config access to be retried Reserved 14 12 RO 0x0 Max PCI Target Retry 11 9 RW 0x1 Indica...

Page 286: ...the number of GRC Reset Reset Counter 2 Register Perst Reset 15 8 Host RW Any Keep tracks of the number of Perst events Reset Counter 1 Register LinkDown Reset 7 0 Host RW Any Keep tracks of the numbe...

Page 287: ...t 0x98 0x9C Name Bits Access Default Value Description Memory Base Register 31 0 RW X Memory value at the location pointed by the Memory Base Register Name Bits Access Default Value Description UNDI R...

Page 288: ...s this field to determine the MSI X table size N which is encoded as N 1 Path i_cfg_func i_cfg_private MSIX_NEXT_CAP_PTR 15 8 RO 0xac This value continues the PCI capability chain It s value specified...

Page 289: ...ntry is used to generate the interrupt message The entry must be one of the first 32 entries even if the function implements more than 32 entries Path i_cfg_func i_cfg_public i_cfg_exp_cap SLOT_IMPLEM...

Page 290: ...ASED_ERR_RPT 15 RO 0x1 Indicate device is conforming to the ECN PCI Express Base Specification Revision 1 1 or subsequent PCI Express Base Specification revisions Path i_cfg_func i_cfg_private unused1...

Page 291: ...ster is set A write of 1 to this bit initiates Function Level Reset The value read by s w from this bit is always 0 MAX_READ_REQ_SIZ 14 12 RW 0 Maximum Read Request Size Depending on the spec internal...

Page 292: ...stream Ports supporting Links wider than x1 and or multiple Link speeds RC Field is implemented EP Not supported and hardwired to 0 Path i_cfg_func i_cfg_public i_cfg_exp_cap DL_ACTIVE_REP 20 RO 0 Dat...

Page 293: ...in common clock mode or not the value reflected by these bits is one of the following ASPM Support These bits are programmable through reg space Path i_cfg_func i_cfg_private ASPM_SUPT 11 10 RO 0x3 Pa...

Page 294: ...otiated link width of the PCI Express link Path i_pl_top i_pl_ltssm NEG_LINK_SPEED 19 16 RO 0 Link Speed These bits indicate the negotiated link speed of the PCI Express link Path i_pl_top i_pl_ltssm...

Page 295: ...ordered sets in the L0s state followed by a single SKP ordered set prior to entering the L0 state and the transmission of 1024 TS1 ordered sets in the L1 state prior to entering the Recovery state Va...

Page 296: ...ction Path i_cfg_func i_cfg_public i_cfg_exp_cap Name Bits Access Default Value Description PHYSICAL_SLOT_NUMBER 31 19 RO 0 Not implemented UNUSED 18 17 RO 0 Not implemented SLOT_POWER_LIMIT_SCAL E 16...

Page 297: ...s Default Value Description DEVICE_STATUS_2 31 16 RO 0 Placeholder for Gen2 Path i_cfg_func i_cfg_public i_cfg_rd_mux Unused 15 11 RO 0 LTR_MECHANISM_ENABLE 10 RW 0 Latency Tolerance Reporting Mechani...

Page 298: ...ABILITY_2 31 0 RO 0 Placeholder for Gen2 Path i_cfg_func i_cfg_private Name Bits Access Default Value Description LINK_STATUS_2 31 17 RO 0 Placeholder for Gen2 CURR_DEEMPH_LEVEL 16 RO 0 curr_deemph_le...

Page 299: ...function has this bit set HW_AUTO_SPEED_DISABL E 5 RO 0 Not Supported and hardwired to 0 Path i_cfg_func i_cfg_public i_cfg_exp_cap ENTER_COMPLIANCE 4 RW 0 S W instructs link to enter compliance mode...

Page 300: ...SLOT_CAPABILITY_2 31 0 RO 0 Not implemented Name Bits Access Default Value Description SLOT_STATUS_2 31 16 RO 0 Not implemented SLOT_CONTROL_2 15 0 RO 0 Not implemented Name Bits Access Default Value...

Page 301: ...RC Error Status 19 RW1CS 0 This bit is set when an ECRC error occurs Malformed TLP Status 18 RW1CS 0 This bit is set when a Malformed TLP error occurs Receiver Overflow Status 17 RW1CS 0 This bit is s...

Page 302: ...rflow Mask 17 RWS 0 Setting this bit will mask Receiver overflow error Unexpected Completion Mask 16 RWS 0 Setting this bit will mask unexpected completion error Completer Abort Mask 15 RWS 0 Setting...

Page 303: ...rols the severity 0 nonfatal 1 fatal Unexpected completion Error Severity 16 RWS 0 This bit controls the severity 0 nonfatal 1 fatal Completer Abort Error Severity 15 RWS 0 This bit controls the sever...

Page 304: ...Status 7 RW1CS 0 This bit is set when a Bad DLLP error occurs Bad TLP Status 6 RW1CS 0 This bit is set when a Bad TLP error occurs Reserved 5 1 RO 0 Receiver Error Status 0 RW1CS 0 This bit is set whe...

Page 305: ...0 ROS 0 This value indicates the bit position within the Uncorrectable Error Status Register 0x104 Name Bits Access Default Value Description Header Byte 0 31 24 ROS The TLP header of the transaction...

Page 306: ...Priority Mailbox Register offset 0x220 0x25c Reload Statistics mail box High Priority Mailbox Register offset 0x260 0x264 Name Bits Access Default Value Description Header Byte 8 31 24 ROS The TLP he...

Page 307: ...sed last Name Bits Access Default Value Description Received BD standard Producer Ring Index 7 0 RW 0 The Receive BD standard Producer Ring Index register contains the index of the next buffer descrip...

Page 308: ...urn Ring 3 Consumer Index Register contains the index of the last buffer descriptor for Receive Return Ring 3 that has been consumed Host software writes this register whenever it updates the return r...

Page 309: ...bit Regs 0x3C88 3 0x2DC 0x35C 0x298 64 bit Regs 0x3C8C 4 0x2E0 0x360 0x2A0 The new Registers are 32 bit 0x3C90 5 0x2E4 0x364 0x2A4 0x3C94 6 0x2E8 0x368 0x2A8 0x3C98 7 0x2EC 0x36C 0x2AC 0x3C9C 8 0x2F0...

Page 310: ...Enable FHDE 23 RW 0 Enable receive Frame Header DMA engine Must be set for normal operation Enable RDE 22 RW 0 Enable RDMA engine Must be set for normal operation Enable TCE 21 RW 0 Enable Transmit D...

Page 311: ...he MAC state machine is reset This is a self clearing bit Name Bits Access Default Value Description Reserved 31 30 RO 0 Reserved 29 RO 0 Interesting packet PME Attention 28 W2C 0 When this bit is set...

Page 312: ...ted with Reg 0x404 29 Interesting packet PME Attention Enable 28 RW 0 When this bit is set an attention will be asserted on an interesting packet match TX Statistics Overrun 27 RW 0 Enable attention w...

Page 313: ...en there is a link and blinks when there is traffic The LED_MODE field must be set to 00 before enabling this bit MAC Mode 13 RW 0 When this bit is set the traffic LED blinks only when traffic is addr...

Page 314: ...n Override Blink Rate bit 31 and Blink Period bits 30 19 fields Override Traffic LED 4 RW 0 If set overrides hardware control of the Traffic LED The Traffic LED will then be controlled via bit 6 and b...

Page 315: ...Address High 15 0 RW 0 Upper 2 bytes of this node s MAC address Name Bits Access Default Value Description MAC Address Low 31 0 RW 0 Lower 4 byte of this node s MAC address Name Bits Access Default V...

Page 316: ...27 16 RW 0 Offset of a frame where the pattern comparison starts Reserved 15 10 RO 0 ACPI Length 9 0 RW 0 Specifies the total number of 64 bit double words inside the MISC_BD memory that are valid fo...

Page 317: ...cription Reserved 31 30 RO 0 Start Busy 29 RW 0 Set this bit to start a transaction While it is high it indicates that the current transaction is still ongoing If enabled generates an attention via EM...

Page 318: ...ceiver device When read a value of 1 indicates the transceiver is linked Name Bits Access Default Value Description Reserved 31 21 RO 0 MII Clock Count 20 16 RW 0Ch Counter to divide CORE_CLK 62 5 MHz...

Page 319: ...block among LAN traffic and APE traffic as below 000 Simple Round Robin 001 Weighted Round Robin 010 Shut off APE transmit stream 011 Shut off LAN transmit stream 1xx Reserved for future use Caution...

Page 320: ...lid SA unless the bit corresponding to the error symptom is set to 1 here in that case the particular error is overlooked and the packet is transmitted in clear text When such a packet is dropped in t...

Page 321: ...was sent Sent XOFF 1 W2C 0 An XOFF flow control frame was sent RX Currently XOFFed 0 RO 0 Received stopped due to flow control Name Bits Access Default Value Description HTX2B Count Down Value 31 24 R...

Page 322: ...path All frames will be accepted and subject to Management filter actions IPV6 Enable 24 RW 0 1 Enable IPv6 RX 0 Disable IPv6 RX which includes IPv6 packet parsing checksum offload and IPv6 RSS RSS_e...

Page 323: ...k by receive MAC on incoming frames Also allows the reception of packets received with RXERR on MII GMII Promiscuous mode 8 RW 0 When set no source address or MC hashing checking will be performed on...

Page 324: ...t be written to clear XOFF received 1 W2C 0 MAC control frame with the PAUSE opcode was received with PAUSE TIME field set to nonzero The bit is sticky and must be written to clear Remote Transmitter...

Page 325: ...ule matches the processor is activated in the queue descriptor for the Receive Queue Placement state machine Mask 26 RW 0 IF set specifies that the value mask field is split into a 16 bit mask instead...

Page 326: ...ding bit in the value field is ignored during the rule match process If bit 26 of the corresponding rule control register is set the field is used as an additional 16 bit value for rule comparison Val...

Page 327: ...FO Almost Empty Threshold 20 16 RW 0xC When the remaining entries of TXFIFO are less than this threshold TXFIFO_almost_empty will be asserted This value is used in conjunction with Buffer Manager Mode...

Page 328: ...ner advertised auto negotiation abilities Reserved 15 11 RO 0 External CRS Detect 10 RO 0 External PHY s CRS output PCS CRS Detect 9 RO 0 Internal PCS blocks CRS output Media Selection mode 8 RO 0 1 S...

Page 329: ...1 to each bit to enable the respective HTX2B protocol filter duplication Note The respective Protocol Filter Enable bit must be 1 for a Duplication to be meaningful Duplicate IPv6 Router Advertisemen...

Page 330: ...Enable IPv6 Router Advertisement 9 RW 0 Enable IPv6 Neighbor Advertisement 8 RW 0 Enable NetBios Packet 7 RW 0 Enable DHCP Server Packet 6 RW 0 Enable DHCP Client Packet 5 RW 0 Enable ARP Packet 4 RW...

Page 331: ...g Protocol Filter setting Name Bits Access Default Value Description table_entry0 31 28 RW 0 The RSS_ring value for entry 0 table_entry1 27 24 RW 0 The RSS_ring value for entry 1 table_entry2 23 20 RW...

Page 332: ...le_entry20 15 12 RW 0 The RSS_ring value for entry 20 table_entry21 11 8 RW 0 The RSS_ring value for entry 21 table_entry22 7 4 RW 0 The RSS_ring value for entry 22 table_entry23 3 0 RW 0 The RSS_ring...

Page 333: ...on table_entry40 31 28 RW 0 The RSS_ring value for entry 40 table_entry41 27 24 RW 0 The RSS_ring value for entry 41 table_entry42 23 20 RW 0 The RSS_ring value for entry 42 table_entry43 19 16 RW 0 T...

Page 334: ...ion table_entry64 31 28 RW 0 The RSS_ring value for entry 64 table_entry65 27 24 RW 0 The RSS_ring value for entry 65 table_entry66 23 20 RW 0 The RSS_ring value for entry 66 table_entry67 19 16 RW 0...

Page 335: ...table_entry88 31 28 RW 0 The RSS_ring value for entry 88 table_entry89 27 24 RW 0 The RSS_ring value for entry 89 table_entry90 23 20 RW 0 The RSS_ring value for entry 90 table_entry91 19 16 RW 0 The...

Page 336: ...e_entry112 31 28 RW 0 The RSS_ring value for entry 112 table_entry113 27 24 RW 0 The RSS_ring value for entry 113 table_entry114 23 20 RW 0 The RSS_ring value for entry 114 table_entry115 19 16 RW 0 T...

Page 337: ...he 2nd byte of the hash_key The bits are in the big endian format Hash_key 23 16 15 8 RW 0 The 3rd byte of the hash_key The bits are in the big endian format Hash_key 31 24 7 0 RW 0 The 4th byte of th...

Page 338: ...its 15 8 This bit should be set to 0 if IPv6 RX is disabled Programmable Extension Header Type 1 Enable 30 RW 0 This bit enables programmable extension header 1 If this bit is clear then the value pro...

Page 339: ...transmission on a particular interface fails due to an internal MAC sublayer transmit error dot3StatsSingleCollisionFrames offset 0x81C A count of successfully transmitted frames on a particular inte...

Page 340: ...gher level protocols requested be transmitted and that were addressed to a multicast address at this sublayer including those that were discarded or not sent iHCOutBroadcastPkts offset 0x874 The numbe...

Page 341: ...Description HTX2B Octets 0x700 0x720 32 Total number of H2B octets HTX2B UCAST PKTS 0x704 0x724 32 Number of H2B unicast frames HTX2B MCAST PKTS 0x708 0x728 32 Number of H2B multicast HTX2B BCAST PKT...

Page 342: ...3StatsFCSErrors offset 0x898 A count of frames received on a particular interface that are an integral number of octets in length and do not pass the FCS check dot3StatsAlignmentErrors offset 0x89C A...

Page 343: ...64 bytes Ifnomorerxbd 0x224C The number of times the NIC overran the Receive Buffer Descriptors Ifindiscard 0x2250 The number of inbound packets selected to be discarded even though an error was not d...

Page 344: ...CXMITERRORS 0x0918 16 SINGLECOL 0x091C 16 MULTICOL 0x0920 16 DEFERREDXMIT 0x0924 16 EXCESSIVECOL 0x092C 16 LATECOL 0x0930 16 IFHCOUTUCAST 0x096C 32 IFHCOUTMCAST 0x0970 32 IFHCOUTBCAST 0x0974 32 CRSERR...

Page 345: ...ion Pre DMA Debug 4 RW 0 When this bit is set Send Data Initiator state machine will be halted if the pre DMA bit of the Send BD is set Hardware Pre DMA Enable 3 RW 0 Enable hardware LSO pre DMA proce...

Page 346: ...ss Default Value Description Reserved 31 1 RO 0 Counters Enable Mask 0 RW 0 Controls whether Class of Service 0 statistics can be updated cleared or flushed Name Bits Access Default Value Description...

Page 347: ...RW 0 Specifies the lower 32bits of the starting address in host memory where the transmit data buffer resides Name Bits Access Default Value Description Upper Host Address 31 0 RW 0 Specifies the uppe...

Page 348: ...t the end of fragmentation No Word Swap 17 RW No Word Swap Set to disable endian word swap on data from PCIE bus Status_dma 16 RW MAC source address Select 15 14 RW This 2 bit field determines which o...

Page 349: ...Bits Access Default Value Description Reserved 31 16 RO 0 VLAN Tag 15 0 RW 0 VLAN Tag to be inserted into the Frame Header if bit 7 of DMA Flags register is set Name Bits Access Default Value Descript...

Page 350: ...e current operation and cleanly halts Until it is completely halted it remains one when read Reset 0 RW 0 When this is set to 1 the Send Data Completion state machine is reset This is a self clearing...

Page 351: ...onsumer index does not rollover for ring sizes 32 64 128 256 Attention Enable 2 RW 0 When this bit is set to 1 an internal attention is generated when an error occurs Enable 1 RW 0 This bit controls w...

Page 352: ...BD Ring Selector Local NIC Send BD 5 Consumer Index RO 0x1454 0x1457 Send BD Ring Selector Local NIC Send BD 6 Consumer Index RO 0x1458 0x145b Send BD Ring Selector Local NIC Send BD 7 Consumer Index...

Page 353: ...to a Single Send Ring 4 0 Unchanged Pass_bit status 4 RW 0 Always return 1 when read Sbdi_rupd_enable 3 RW 0 Attention Enable 2 RW 0 When this bit is set to 1 an internal attention is generated when a...

Page 354: ...roducer Index RO 0x180c 0x180f Send BD 2 Producer Index RO 0x1810 0x1813 Send BD 3 Producer Index RO 0x1814 0x1817 Send BD 4 Producer Index RO 0x1818 0x181b Send BD 5 Producer Index RO 0x181c 0x181f S...

Page 355: ...ugh there are other factors which might further limit the DMA size This parameter uniformly applies to all 16 Send Rings This parameter is meaningful only in the Multiple Send Ring mode 0x1800 5 1 Tab...

Page 356: ...lt Value Description Reserved 31 3 RO 0 Attention Enable 2 RW 0 When this bit is set to 1 an internal attention is generated when an error occurs Enable 1 RW 1 This bit controls whether the Send BD Co...

Page 357: ...n Enable 2 RW Enable attention for zero class field Enable 1 RW 1 This bit controls whether the Receive List Placement state machine is active or not When set to 0 it completes the current operation a...

Page 358: ...31 15 RO 0 Default Interrupt Distribution Queue 14 13 RW 0 Default interrupt distribution queue Number within a class of service group when the frame has errors is truncated or is a non IP frame Bad...

Page 359: ...choose receive return ring in terms of RSS hash value instead of RC class when both RSS and RC rules are matched Default is to give priority to RC RC Return Ring Enable 24 RW 0x0 1 Enable receive pack...

Page 360: ...et 0x2128 Receive Selector List 4 Count Registers offset 0x2138 Receive Selector List 5 Count Registers offset 0x2148 Receive Selector List 6 Count Registers offset 0x2158 Receive Selector List 7 Coun...

Page 361: ...ctor List 10 Count Registers offset 0x2198 Receive Selector List 11 Count Registers offset 0x21a8 Receive Selector List 12 Count Registers offset 0x21b8 Receive Selector List 13 Count Registers offset...

Page 362: ...ing 2048 Jumbo Producer Ring 1024 Receive Return Ring 4096 When this bit is 0 following are the maximum allowable Receive Ring sizes Standard Producer Ring 512 Jumbo Producer Ring 256 Receive Return R...

Page 363: ...Receive BD 3 RW Enables frame size is too large to fit into one Receive BD attention Reserved 2 RO 0 Enable 1 RW 1 This bit controls whether the Receive Data and Receive BD Initiator state machine is...

Page 364: ...o force an internal index reset request Bit 8 combining with 31 15 bit map indicates which IOV index group to be reset The function is identical to bit 1 hardware flush reset This bit is self clear Re...

Page 365: ...value 0x0 in this register effectively zeroes this timer count Name Bits Access Default Value Description IOV Flush Timer 31 0 RW 0x0 This value will be loaded into a count down counter triggered by...

Page 366: ...g element The host ring address is in host address format Name Bits Access Default Value Description Max Length 31 16 RW 0 Specifies the number of entries for Jumbo ring based on bit mask Supported va...

Page 367: ...and a copy of the controller s receive BD consumer index The local return ring producer index is set to the value placed in the DMA descriptor The local controller receive return consumer index is als...

Page 368: ...consumer index is also set to the value placed in the DMA descriptor Receive Data and Receive BD Initiator Hardware Diagnostic Register offset 0x24C0 B2HRX Byte count Statistics Count offset 0x24D0 B2...

Page 369: ...Default Value Description B2HRX DROP PKT 31 0 CORW 0 Host B2HRX packet drop count due to empty RBD Name Bits Access Default Value Description B2HRX DROP OCTETS 31 0 CORW 0 Host B2HRX packet drop byte...

Page 370: ...0 B2HRX APE Drop Packet Count offset 0x24F8 B2HRX APE Drop Packet Byte Count offset 0x24FC Name Bits Access Default Value Description B2HRX DROP PKT 31 0 CORW 0 APE B2HRX packet drop count due to empt...

Page 371: ...lt Value Description Reserved 31 3 RO 0 Attention Enable 2 RW 0 When this bit is set to 1 an internal attention is generated when an error occurs Enable 1 RW 1 This bit controls whether the Receive Da...

Page 372: ...ntrols whether the Receive BD Initiator state machine is active or not When set to 0 it completes the current operation and cleanly halts Until it is completely halted it remains one when read Reset 0...

Page 373: ...t 0x2C1C All registers reset are core reset unless specified Standard Replenish LWM Register offset 0x2D00 Name Bits Access Default Value Description Reserved 31 10 RO 0 BD Number 9 0 RW 0 Number of b...

Page 374: ...h is request triggered Recommended Settings Non IOV mode STD LWM 32 1 4 of total RBDs IOV mode STD LWM 16 1 2 of total RBDs Name Bits Access Default Value Description Legacy 31 8 RU 0x0 Unused Repleni...

Page 375: ...e following Space available in the respective BD cache Standard or Jumbo Replenish Threshold Number of BDs made available in the Host memory based Ring Programmed Value of this Field Name Bits Access...

Page 376: ...Current Jumbo Received BD have been fetched by RDMA module and are available for incoming RX packets Name Bits Access Default Value Description Reserved 31 9 RO 0 NIC Standard Receive BD Producer Inde...

Page 377: ...0x0 Reserved 12 11 RW 0x0 Link Aware Power mode Enable 10 RW 0x0 Link Aware Power mode Enable 1 Enable 0 Disable Link Idle Power mode Enable 9 RW 0x0 Link Idle Power mode Enable 1 Enable 0 Disable Res...

Page 378: ...er than intended clock speed Name Bits Access Default Value Description Reserved 31 21 DC 0x000 MAC Clock Switch 20 16 RW 10111 Software Controlled MAC Core Clock Speed Select 00000 Core 62 5 MHz GPHY...

Page 379: ...clock speed Name Bits Access Default Value Description Reserved 31 21 DC 0x000 MAC Clock Switch 20 16 RW 10001 Software Controlled MAC Core Clock Speed Select 00000 Core 62 5 MHz GPHY DLL 2 00001 Core...

Page 380: ...rammed to a different value only for engineering debug Name Bits Access Default Value Description Reserved 31 21 DC 0x0 MAC Clock Switch 20 16 RW 0x0 Software Controlled MAC Core Clock Speed Select 00...

Page 381: ...11 Software Controlled MAC Core Clock Speed Select 00001 Core 60 0 MHz Alt Source 2 00011 Core 30 0 MHz Alt Source 4 00101 Core 15 0 MHz Alt Source 8 00111 Core 7 5 MHz Alt Source 16 01001 Core 3 75 M...

Page 382: ...Core Clock Speed Select 00001 Core 60 0 MHz Alt Source 2 00011 Core 30 0 MHz Alt Source 4 00101 Core 15 0 MHz Alt Source 8 00111 Core 7 5 MHz Alt Source 16 01001 Core 3 75 MHz Alt Source 32 10001 Cor...

Page 383: ...clock speed override BCM5719 Force APE FCLK Disable 28 RW 0x0 APE FCLK clock Disable 1 Disable APE FCLK clock 0 Enable APE FCLK clock BCM5719 Force APE HCLK Disable 27 RW 0x0 APE HCLK Disable 1 Disab...

Page 384: ...z CK25 10011 12 5 MHz CK25 2 10101 6 25 MHz CK25 4 10111 3 125 MHz CK25 8 11001 1 563 MHz CK25 16 11110 83 MHz BCM5719 00000 62 5 MHz NCSI DLL 2 10001 25 0 MHz CK25 10011 12 5 MHz CK25 2 10101 6 25 MH...

Page 385: ...30 21 DC 0x000 APE Deep Sleep FCLK Switch 20 16 RW 10001 Software Controlled APE Clock Speed Select 00001 60 0 MHz Alt Source 2 00011 30 0 MHz Alt Source 4 00101 15 0 MHz Alt Source 8 00111 7 5 MHz A...

Page 386: ...I DLL 2 10001 Core 12 5 MHz CK25 2 10011 Core 6 25 MHz CK25 4 10101 Core 3 125 MHz CK25 8 10111 Core 1 563 MHz CK25 16 For 5718 Software Controlled MAC Core Clock Speed Select00000 Core 62 5MHz GPHY D...

Page 387: ...APE HCLK Disable 1 Disable APE HCLK clock 0 Enable APE HCLK clock Name Bits Access Default Value Description Reserved 31 RO For 5719 four port devices the bit31 will be used by FUNC_NUMBER For 5718 57...

Page 388: ...RO 1 Locked 0 Not locked WOL ACPI Detection Enable Status of Port 0 15 RO 1 ACPI detection enabled 0 ACPI detection disabled WOL Magic Packet Detection Enable Status of Port 0 14 RO 1 Magic Packet De...

Page 389: ...status APE FCLK Disable Status 24 RO APE FCLK clock disable status PERST_N status 23 RO PERST_N status Reserved 22 21 DC 0x0 MAC Clock Switch Status 20 16 RO MAC Core Clock Speed Select Status Reserve...

Page 390: ...Guide Broadcom January 29 2016 5718 PG108 R Page 390 Reserved 15 13 DC 0x0 APE Clock Switch Status 12 8 RO APE Clock Speed Select Status Flash Clock Switch Status 7 5 RO Flash Clock Speed Select Stat...

Page 391: ...k Status BCM5719 GPHY PLL Lock Status 23 RO 0x0 GPHY PLL Lock Status BCM5719 PCIE SERDES PLL Lock Status 22 RO 0x0 PCIE SERDES PLL Lock Status BCM5719 NCSI PLL Test Select 21 18 RW 0x0 NCSI PLL Test S...

Page 392: ...tion will be powered down GPHY PCIE IPSEC APE This bit is cleared by a rising edge of PERST_L BCM5717 and BCM5718 Reserved 3 DC 0x0 CPMU Register Software Reset 3 RW SC 0x0 Software reset for resettin...

Page 393: ...tive to non active Unit is in number of CPMU clock cycles Range up to 232 CPMU clock cycles Default Value 10 CPMU CLK multiplied by given Core CLK scale parameter below x1 00000 Core 62 5 MHz GPHY DLL...

Page 394: ...rgy_det_apd from GPHY core 0 use output from the energy debounce logic Select HW_Energy_Det 8 RW 0x1 This bit selects the source of the System Energy_Det output This bit is allows the boot code to res...

Page 395: ...ce High 1 Disable De bounce High Energy_Det De bounce High Limit 3 2 RW 0x0 This parameter is used to control the debounce limit of the GPHY Energy_Det_APD signal going high 00 128 million CPMU clocks...

Page 396: ...lt 25088 CPMU clocks 1ms if CPMU clock frequency is 25 MHz BCM5719 NCSI PLL Lock Timer 31 16 RW 0xF This parameter is used to preset the NCSI PLL Lock Timer This timer is always enabled Unit is in num...

Page 397: ...a bit shall have no effect Reading this field may return zero or more bits with value 1 Each bit with value 1 indicates a pending request Name Bits Access Default Value Description Reserved 31 16 DC 0...

Page 398: ...de enable 0 RW 0x0 Enable SerDes test mode on mission board Name Bits Access Default Value Description Reserved 31 27 DC 0x0 Readable and writeable reserved bits APE Status 26 RW 0 This bit is used by...

Page 399: ...PLLisUp signal drive 12 RW 0x0 When 0 force the PLLisUp signal to be 1 When 1 let the hardware drive the PLLisUp signal PCIE pcie_tmux_sel 3 2 11 10 RW 0x0 Reserved 9 RW 0 Capability version for compl...

Page 400: ...by 10 Clock frequency of 125 MHz 00001011 divide by 11 Clock frequency of 113 6 MHz 11111111 divide by 255 Clock frequency of 4 9 MHz Reserved 11 DC 0 Flash Idle Clock Policy 10 8 RW 0x2 Software Cont...

Page 401: ...entering link idle mode and host access mode DBU Idle 21 RW 0 Link idle Host Access condition control 1 disable this idle condition when entering link idle mode and host access mode 0 enable this idle...

Page 402: ...ink idle mode and host access mode RXMAC FIFO empty 11 RW 0 Link idle Host Access condition control 1 disable this idle condition when entering link idle mode and host access mode 0 enable this idle c...

Page 403: ...e mode and host access mode GRC Idle 3 RW 0 Link idle Host Access condition control 1 disable this idle condition when entering link idle mode and host access mode 0 enable this idle condition when en...

Page 404: ...C Readable and writeable reserved bits PCIE Idle 24 RO Idle Status 1 Idle 0 Busy APE ATP Empty 23 RO APE ATPM Idle 22 RO DBU Idle 21 RO NVM Idle 20 RO SBDI Idle 19 RO RBDI Idle 18 RO MB Idle 17 RO Res...

Page 405: ...scription Reserved 31 6 RW 0 Low power IDDQ mode 5 RW 0 1 Enable to put all ports in GPHY mode during low power IDDQ to select GPHY mode to save power 0 SerDes mode in low power IDDQ mode by default d...

Page 406: ...circuit uses the earliest receive packet indicator after mac address filtering circuit Each increment increases the delay by 10 240 S 0x0 no delay 0x1 10 24 s delay 0x2 20 48 s delay 0xFF 2621 44 s d...

Page 407: ...ex Detection Enable 6 RW 0x0 This bit allows CPMU to use the send consumer and producer equal term to determine EEE mode RX CPU Allow LPI Enable 5 RW 0x0 Enable Control bit allocated for RX CPU to all...

Page 408: ...n logic UART is idle No on going MDIO access IE is in L0s L1 or L2 state Reserved 23 4 RW 0x0 MDIO Idle 3 RW 0x0 MDIO status control 1 disable this idle condition from the EEE idle detection logic 0 e...

Page 409: ...ers in APE subsystem for TX is empty LAN TX Packet Buffer Empty 0 RO 0x0 Internal packet buffers in LAN core for TX is empty Name Bits Access Default Value Description EEE Mode Entering Counter 31 0 R...

Page 410: ...0 Stop the accumulation process of the PDRIVE samples This effectively disables the cur_meas block and freezes all values of registers This bit can be set to stop the register updates for register rea...

Page 411: ...RO 0x0 Please refer to 0x36D4 1 0 Name Bits Access Default Value Description Lower 32 bit of Current Measurement Count 31 0 RO 0x0 Please refer to 0x36D4 1 0 Note This register is for BCM5719 BCM5720...

Page 412: ...1S 0x0 Reading this field shall return a maximum of one set bit at any time The set bit shall point to the lock owner If the Mutex is not locked a read shall return a value 0x0000 Writing a 1 to the...

Page 413: ...e a status without a corresponding interrupt event Reserved 10 RO 0 When set the TX Host Coalescing Tick counter initializes to the idle state and begins counting only after a transmit BD event is det...

Page 414: ...receive event only if the Receive Max Coalesced BD value is reached Of course status block updates for other reasons e g transmit events will also include any updates to the receive indices By settin...

Page 415: ...red to be in the expired state Once the counter is in the expired state a status block update will occur if a transmit event has occurred since the last status block update In this case a transmit eve...

Page 416: ...Coalesced BD Count Register offset 0x3C10 This register contains the maximum number of receive return ring BDs that must filled in by the device before the device will update the status block due to a...

Page 417: ...eceive Max Coalesced BD Count Register for VRQ 0 0x3C10 Receive Max Coalesced BD Count Register for VRQ 1 0x3D88 Receive Max Coalesced BD Count Register for VRQ 2 0x3DA0 Receive Max Coalesced BD Count...

Page 418: ...and interrupts that occur due to transmitting packets This can increase performance in hosts that are under a high degree of stress and whose RISCs are saturated due to handling a large number of int...

Page 419: ...D Count During Interrupt Register for VRQ 6 0x3E08 Receive Max Coalesced BD Count During Interrupt Register for VRQ 7 0x3E20 Receive Max Coalesced BD Count During Interrupt Register for VRQ 8 0x3E38 R...

Page 420: ...BD Count During Interrupt Register for TXQ 6 0x3E0C Send Max Coalesced BD Count During Interrupt Register for TXQ 7 0x3E24 Send Max Coalesced BD Count During Interrupt Register for TXQ 8 0x3E3C Send...

Page 421: ...egister offset 0x3D28 Status Block 7 Host Address Register offset 0x3D30 Status Block 8 Host Address Register offset 0x3D38 Status Block 9 Host Address Register offset 0x3D40 Status Block 10 Host Addr...

Page 422: ...nd BD Initiator 31 W2C The Send BD Initiator state machine has caused an attention Send BD Completion 30 W2C The Send BD Completion state machine has caused an attention Send BD Ring Selector 29 W2C T...

Page 423: ...e has reached the mbuf low water threshold Reserved 5 0 RO 0 Table 108 NIC Receive BD Consumer Index Register offset 0x3C50 0x3C58 Name Bits Access Default Value Description Reserved 31 8 RO 0 NIC Jum...

Page 424: ...d the Receive Data and Receive BD Initiator state machines which is used to keep track of the receive BDs that have been DMAed to the NIC NIC Diagnostic Return Ring 0 Producer Index Register offset 0x...

Page 425: ...3CC0 The register keeps track of the NIC local copy of the send BD ring consumer not the host copy which is DMAed by the Host Coalescing engine to the host It is shared between the Send BD Initiator a...

Page 426: ...gh the original memory arbitration logic Reserved 26 21 RO 0 DMAW2 Addr Trap 20 RW 0 DMA Write 2 Memory Arbiter request trap enable Reserved 19 17 RO 0 SDI Addr Trap Enable 16 RW 0 Send Data Initiator...

Page 427: ...19 17 RO 0 SDI Addr Trap 16 W2C 0 Send Data Initiator Memory Arbiter request trap Reserved 15 13 RO 0 RDI2 Addr Trap 12 W2C 0 Receive Data Initiator 2 Memory Arbiter request trap RDI1 Addr Trap 11 W2C...

Page 428: ...ention Enable 31 RW 0x1 1 Enable the EMAC TXFIFO underrun prevention during LSO offload operation It will change the arbitration algorithm of TXMBUF read requests to round robin among CPU PCIE RDMA an...

Page 429: ...set to 0 it completes the current operation and cleanly halts Until it is completely halted it remains one when read Reset 0 RW 0 When this bit is set to 1 the Buffer Manager state machine is reset T...

Page 430: ...be available before normal operation is restored to the Read DMA Engine and or the RX MAC RX RISC MBUF Cluster Allocation Request Register offset 0x441C The RX RISC MBUF Cluster Allocation Request re...

Page 431: ...RXMBUF counts BM Hardware Diagnostic 3 Register offset 0x4454 This 32 bit register provides debug information on the RXMBUF pointer Name Bits Access Default Value Description Reserved 31 26 RO 0 Last...

Page 432: ...ister offset 0x4458 Next RXMBUF Allocation pointer 14 9 RO 0 The next RXMBUF that is to be allocated Name Bits Access Default Value Description Reserved 31 9 RO 0 MBUF Threshold 8 0 RW 0 Defines the i...

Page 433: ...this bit is set the Send Data Completion State Machine will be halted if the Post DMA bit of the Send BD is set Address Overflow Error Logging Enable 25 RW 0 This bit when set enables the address ove...

Page 434: ...ead DMAPCI FIFO Underrun Attention Enable 7 RW 0 Enable Read DMA PCI FIFO Underrun Attention Read DMA PCI FIFO Overrun Attention Enable 6 RW 0 Enable Read DMA PCI FIFO Overrun Attention Read DMA PCI H...

Page 435: ...ss above the same multiple of 4 GB i e the host memory address transitions from 0xXXXXXXXX_FFFFFFFF to 0xYYYYYYYY_00000000 in a single read This is a fatal error Read DMA PCI Parity Error 4 W2C 0 Read...

Page 436: ...low Clock Fix Disable 3 RW 0 When cleared it enables the fix to cover a corner case in the link idle mode to allow the DMA Read request to be generated when the core clock is transitioning from slow t...

Page 437: ...x in A1 for DMA Read engine miscalculation of TXMBUF Available Space 25 RW 0 0 Enable fix 1 Disable fix Disable fix in A1 for DMA Read Underrun when running Core Clk same speed as TL Clock when CLKREQ...

Page 438: ...ble_fast_ return 9 RW 0 0 Enable fix 1 Disable fix sbd_8b_less_fix_enable 8 RW 0 0 Enable fix 1 Disable fix Enable hardware fix for the wrong TCP checksum when LSO send out 7 RW 0 The fix involves wip...

Page 439: ...1 entry time to a value on the order of 1ms is recommended and may prevent this issue from occurring See register 0x7d28 Enable hardware fix 2 RW 1 Set to 1 to enable fix for Tx Read DMA lock up issue...

Page 440: ...to interrupt the internal CPU and the DMA Read Engine will lock up after detecting this error So it is recommended that this bit should not be set by firmware or software 1 Enable Address Overflow Err...

Page 441: ...is reset This is a self clearing bit Name Bits Access Default Value Description rdmad_length_b_0 31 16 RO 0 Reserved 15 11 RO 0 Read DMA PCI X Split Transaction Timeout Expired 10 W2C 0 Read DMA PCI X...

Page 442: ...be generated when the core clock is transitioning from slow to fast Stop communicating after heavy stress Fix 2 RO 0 When set this bit enables the fix for DMA FIFO overrun occurs if a large number of...

Page 443: ...on the order of 1ms is recommended and may prevent this issue from occurring See register 0x7d28 Enable hardware fix for clock switching problem 3 RO 1 Set to 1 to enable fix for clock switching prob...

Page 444: ...PCIe Maximum Read Request Size MRRS field of the PCIe Device Status Control Register 0xB4 Reserved 15 11 RO 0 Read DMA PCI X Split Transaction Timeout Expired Attention Enable 10 RO 0 Enable read DMA...

Page 445: ...nger Than DMA Length Error 9 W2C 0 Read DMA Local Memory Write Longer Than DMA Length Error Read DMAPCI FIFO Overread Error 8 W2C 0 Read DMA PCI FIFO Overread Error PCI read longer than DMA length Rea...

Page 446: ...ogrammable Extension Header Type 1 Enable 30 RO 0 This bit enables programmable extension header 1 If this bit is clear then the value programmed in bits 7 0 of this register will be ignored If this b...

Page 447: ...oning from slow to fast Hardware fix enable for DMA FIFO Overrun 2 RO 0 When set this bit enables the fix for DMA FIFO overrun occurs if a large number of Rx BDs are fetched while the Tx MBUF is full...

Page 448: ...1 to L0 with Clkreq Enable 4 RO 1 Set to 1 to enable fix for clock request gap problem of Tx Read DMA lock up issue Note that increasing the ASPM L1 entry time to a value on the order of 1ms is recomm...

Page 449: ...for status words HC Word Swap 16 RW 0 Word swap control for status words BD Byte Swap 15 RW 0 Byte swap control for return BDs BD Word Swap 14 RW 0 Word swap control for return BDs Data Byte Swap 13 R...

Page 450: ...cleanly halts Until it is completely halted it remains 1 when read Reset 0 RW 0 When this bit is set to 1 the Write DMA state machine is reset This is a self clearing bit Name Bits Access Default Valu...

Page 451: ...by reset Cleared by Watchdog interrupt Halt RX RISC 10 RW 0 Set by TX RISC or the host to halt the RX RISC Cleared on reset and Watchdog interrupt Flush Instruction Cache 9 WO 0 Self clearing bit whic...

Page 452: ...tes of SRAM force the RX RISC to halt and cause bit 3 in the RX RISC state register to be latched Cleared on reset and Watchdog interrupt Single Step RX RISC 1 RW 0 Advances the RX RISC s PC for one c...

Page 453: ...ived from the Global Resources block indicating that this processor accessed a register location that triggered a software trap The GRC registers are used to configure register address trapping Memory...

Page 454: ...istics Name Address Size Description 1 IFHCOUTOCTETS 0x0A00 32 Queue 1 Transmit IFHCOUTUCAST 0x0A04 32 Queue 1 Transmit IFHCOUTMCAST 0x0A08 32 Queue 1 Transmit IFHCOUTBCAST 0x0A0C 32 Queue 1 Transmit...

Page 455: ...eive Reserved 0x0BF4 32 VRQ 16 Receive IFHCINUCASTPKTS 0x0BF8 32 VRQ 16 Receive IFHCINMULTICASTPKTS 0x0BFC 32 VRQ 16 Receive Table 111 Default Drop VRQ Statistics Offset 0x09F7 0x09D0 VRQ Statistics N...

Page 456: ...atch Address Reg Term D Product Term C Reserved 23 22 RO 0 Activate Perfect Match in this Term 21 RW 0 Write a 1 in this field to activate the Perfect Match Address Reg selected by field 20 16 Perfect...

Page 457: ...B Activate Product Term B 15 RW 0 Write a 1 to activate this whole Product Term AND OR 14 RW 0 0 Perfect Match Addr VRQ Filter Set 1 Perfect Match Addr VRQ Filter Set Activate VRQ Filter Set in this T...

Page 458: ...ister Offset 0x560 Name Bits Access Default Value Description Reserved 31 18 RO 000 Reserved VRQ Enable Bit Map 17 0 RW 0x0000 When a bit position is written 1 the respective VRQ is enabled and is cap...

Page 459: ...D8 0x358 0x290 0x3C88 3 0x2DC 0x35C 0x298 0x3C8C 4 0x2E0 0x360 0x2A0 The new Registers are 32 bit 0x3C90 5 0x2E4 0x364 0x2A4 0x3C94 6 0x2E8 0x368 0x2A8 0x3C98 7 0x2EC 0x36C 0x2AC 0x3C9C 8 0x2F0 0x370...

Page 460: ...It is also used by the Host Coalescing engine to determine if the host is in the interrupt handler If it is non zero this indicates the host is in the interrupt handler If it is zero this indicates t...

Page 461: ...r descriptor for the extended producer ring that will be produced in the host for the NIC to DMA into NIC memory Host software writes this register whenever it updates the extended producer ring This...

Page 462: ...es this register whenever it updates the given send ring This register must be initialized to 0 The host producer indices may not be used at the same time as the NIC producer indices When multiple TXQ...

Page 463: ...4 Send BD Ring Producer Index Register for Ring 3 offset 0x5988 Send BD Ring Producer Index Register for Ring 4 offset 0x598C Send BD Ring Producer Index Register for Ring 5 offset 0x5990 Send BD Ring...

Page 464: ...et Host Coalescing FTQ 10 RW 0 Set this bit to reset the Host Coalescing flow through queue When set to 0 this flow through queue is ready for use This bit is self clearing Reset Send Data Completion...

Page 465: ...f the RDIQ FTQ entry When the Valid bit is 1 and the Pass bit is 0 the CPU can take the RXMBUF cluster pointers to access the received Packet When the CPU writes a 1 to the Skip bit the hardware will...

Page 466: ...et Tail RXMBUF Pointer 8 0 RO 0 Specifies the last MBUF of the RXMBUF cluster for the received packet Name Bits Access Default Value Description Priority 31 30 RW 0 Sets the priority of the MSI engine...

Page 467: ...RW 0 PCI parity error attention enable PCI Master Abort Attn 3 RW 0 PCI master abort attention enable PCI Target Abort Attn 2 RW 0 PCI target abort attention enable Enable 1 RW 1 This bit controls wh...

Page 468: ...hen read Reset 0 RW 0 When this bit is set to 1 the DMA Completion state machine is reset This is a self clearing bit Name Bits Access Default Value Description Pcie TL DL PL mapping bit 31 RW 0 Bit 3...

Page 469: ...btain the correct checksum the driver must seed the TCP UDP checksum field with the pseudo header checksum Time Sync Mode Enable 19 RW 0 Write 1 to this bit to enable Time Sync Mode HTX2B Feature Enab...

Page 470: ...wards Legacy 7 0 Defined by Legacy Byte Swap for B2HRX Data 7 RW 0 This bit must be 1 for proper B2HRX operation in case of Little Endian Host machines Word Swap for B2HRX Data 6 RW 0 This bit must be...

Page 471: ...PowerState mirrors the PMSCR register Bond ID 16 13 RO ID 3 0 Bond ID Reserved 12 8 RO 0 Timer Prescaler 7 1 RW 1111111b Local Core clock frequency in MHz minus 1 which should correspond to each advan...

Page 472: ...4 RO 0 Interrupt on Attention 3 RW 0 If set the host will be interrupted when any of the attention bits in the CPU event register are asserted Set Interrupt 2 WO 0 If Interrupt Mailbox 0 contains a no...

Page 473: ...CPU needs attention MAC Attention 25 RO 0 MAC needs attention Reserved 24 RO 0 SW Event 10 23 RW 0 SW Event 10 is set High Priority Mailbox 22 RO 0 First 32 Mailbox registers have been updated Low Pri...

Page 474: ...provide a 1 if that register owns the semaphore and a 0 otherwise To obtain the semaphore the normal operation is a loop containing a write 0 followed by a read Exit the loop when the read returns non...

Page 475: ...te the address into the address register ensuring that the write bit is clear Loop reading the address register until the complete bit is set When it is the write is complete Clear the complete bit by...

Page 476: ...ble 15 RW 0 ASF Location 14 14 RW 0 Reserved 13 RW 0 ASF Location 13 12 RW 0 Unused SDI 11 RW 0 SDC Post TCP segmentation 10 RW 0 SDI Pre TCP segmentation 9 RW 0 RDIQ FTQ Received an ASF 8 RW 0 ASF Lo...

Page 477: ...gets reset by Power On Reset MISC 1 Bits 23 1 RW 0 Reserved RW bits that get reset by GRC Reset Reserved 0 RO 0 Name Bits Access Default Value Description Fastboot Enable 31 RW 0 This bit is used by...

Page 478: ...de This bit is NOT Self Clear Software need to generate a pulse by writing a 1 followed by 0 in order to restart the PLL It s for debugging purposes Select Core Clock Override 29 RW 0 1 Enable switchi...

Page 479: ...0 RW X Name Bits Access Default Value Description Reserved 31 24 RW 0x0 Memory TM control retrybuf 23 16 RW 0x00 TM control of retry buffer Memory TM control txmbuf 15 8 RW 0x00 TM control for txmbuf...

Page 480: ...to be d word aligned Name Bits Access Default Value Description Reserved 31 28 RW 0x0 Reserved WDMA FIFO tmb control 27 26 RW 0x00 TM control for WDMA engine memory WDMA FIFO tma control 25 24 RW 0x0...

Page 481: ...l 3 2 RW 0x00 TM control for LSO RDMA engine LSO RDMA FIFO tma control 1 0 RW 0x00 TM control for LSO RDMA engine Name Bits Acces s Default Value Description Reserved 31 28 RW 0 MSI MSI X Vector Write...

Page 482: ...a platform must design in these pins and have individual BootCode or firmware configure this register and APE GPIO register accordingly Name Bits Access Default Value Description EAV Reference Count l...

Page 483: ...is mapped to 1588 input output via this field 000 Do not use APE_GPIO n pin 001 Reserved 010 Reserved 011 Reserved 100 Use as Snap Shot 0 Input Trigger 101 Use as Snap Shot 1 Input Trigger 110 Use as...

Page 484: ...as snapshot by TimeSync APE GPIO Name Bits Access Default Value Description Watchdog LSB Value 31 0 RW 0x0000 See TX Time Watchdog MSB 0 Reg offset 0x691C Name Bits Access Default Value Description En...

Page 485: ...hich equates to the precision of the EAV Reference Count If bit 31 1 the required Timesync APE GPIO toggles as soon as EAV Reference Count 62 0 increments to match this 63 bit value Note Setting this...

Page 486: ...de Broadcom January 29 2016 5718 PG108 R Page 486 EAV Ref Count Snapshot MSB 1 Reg Offset 0x6934 Name Bits Access Default Value Description EAV Reference Count Snap shot Upper half 31 0 RO U MSB of th...

Page 487: ...device to clear the write enable bit in the device status register This command is used for devices with a write protection function Reserved Write Enable Command 16 RO 0 The write enable command bit...

Page 488: ...bit has completed The done bit will be cleared while the command is in progress The done bit will stay asserted until doit is reasserted or the done bit is cleared by writing a 1 to the done bit The...

Page 489: ...11b 2048 bytes 100b 4096 bytes 101b 264 bytes 110b reserved 111b reserved Reserved 27 RO Reserved Safe Erase 26 RO 0 Flash Size strap bit 3 25 RO Pin Protect Mode strap bit 2 24 RO pin Strap bit 5 23...

Page 490: ...O 0 Reserved Pass mode 2 RO 0 Buffer mode 1 RW Pin Enable SSRAM Buffered Interface mode Flash mode 0 RW Pin Enable Flash Interface mode Name Bits Access Default Value Description Reserved 31 24 RO 0 S...

Page 491: ...ffer Write Command 23 16 RO 0 Write Command 15 8 RW 0x82 if AT26DFXX 0x82 if AT45DBXX 0x0A if STM25PEXX 0x0A if STM45PEXX Command to write a series of bytes into a selected page in the Flash device No...

Page 492: ...bitration won bit 1 see Bit 8 ARB_WON0 ARB_WON0 8 RO 0 When req0 arbitration is won this bit will be read as 1 When an operation is complete then Req_clr0 must be written to clear bit At that point th...

Page 493: ...d issues NVM Access Write Enable 1 RW 0 When 1 allows the NVRAM write command to be issued even if the NVRAM write enable bit21 of the mode control register 0x6800 NVM Access Enable 0 RW 0 When 0 prev...

Page 494: ...RO 0x1F AT45DB011D 5 b0_0100 AT45DB021D 5 b0_0011 AT45DB041D 5 b0_0000 STM25PE10 5 b0_1011 STM25PE20 5 b0_1010 STM25PE40 5 b0_1000 STM45PE10 5 b0_1100 STM45PE20 5 b0_1101 STM45PE40 5 b0_1110 Unsupport...

Page 495: ...iver contains the set of registers shown in the tables below BCM5718 Family MII Bus PHY Addressing Table 119 BCM5717 Port 0 Port 1 Block PHY Address Block PHY Address GPHY 0x01 GPHY 0x02 Table 120 BCM...

Page 496: ...Auto_Negot_Advertisement_Register 05h Auto_Negot_Link_Partner_Ability_Base_Pg_Register 06h Auto_Negot_Expansion_Register 07h Auto_Negot_Next_Page_Transmit_Register 08h Auto_Negot_Link_Partner_Ability...

Page 497: ...08 R Page 497 18h Auxiliary_Control_Register Shadow Registers 001 10 BASE T 010 Power Control 011 IP Phone 100 Misc Test 101 Misc Test 2 110 Manual IP Phone seed 111 Misc Control 19h Auxiliary_Status_...

Page 498: ...Control 2 01101 LED Selector 1 01110 LED Selector 2 01111 LED GPIO Control Status 10000 Reserved 10001 SerDes 100 FX Status 10010 SerDes 100 FX Test 10011 SerDes 100 FX Control 10100 External SerDes...

Page 499: ...tended Control Reg 11h PHY Extended Status Reg 12h Receive Error Counter Reg 13h False Carrier Sense Error Counter Reg 14h Local Remote Receiver Not Ok Counter Reg 15h DSP Coefficient Read Write Port...

Page 500: ...s 01 100 Mbit s 00 10 Mbit s 12 AUTONEGOTIATION_ENAB LE RW 1 1 auto negotiation enabled 0 auto negotiation disabled 11 POWER_DOWN RW 0 1 low power mode 0 normal operation 10 ISOLATE RW 0 1 isolate PH...

Page 501: ...SE T2 full duplex capable 9 100BASE_T2_HALF_DUPLEX_ CAPABLE RO L 0 1 100BASE T2 half duplex capable 0 not 100BASE T2 half duplex capable 8 EXTENDED_STATUS RO H 1 1 extended status information in regis...

Page 502: ...ice revision number metal programmable Bit Name RW Default Description 15 NXT_PAGE RW 0 1 next page ability supported 0 next page ability not supported 14 RESERVED RW 0 write as 0 ignore on read 13 RE...

Page 503: ...USE_CAPABLE RO 0 1 link partner is capable of Pause operation 0 link partner not capable of Pause operation 9 100BASE_T4_CAPABLE RO 0 1 link partner is 100BASE T4 capable 0 link partner is not 100BASE...

Page 504: ...ext page able 0 local device is not next page able 1 PAGE_RECEIVED RO LH 0 1 new link code word has been received 0 new link code word has not been received 0 LINK_PARTNER_AUTONEG_ABILITY RO 0 1 link...

Page 505: ...efault Description 15 13 TEST_MODE RW 000 1xx Test Mode 4 011 Test Mode 3 010 Test Mode 2 001 Test Mode 1 000 Normal Operation 12 MASTER_SLAVE_CONFIG_ ENABLE RW 0 1 enable Master Slave manual config v...

Page 506: ...tner is not 1000BASE T full duplex capable 10 LINK_PARTNER_1000BASE_T _HALF_DUPLEX_CAPABLE RO 0 1 link partner is 1000BASE T half duplex capable 0 link partner is not 1000BASE T half duplex capable 9...

Page 507: ...L 0 1 1000BASE X half duplex capable 0 not 1000BASE X half duplex capable 13 1000BASE_T_FULL_DUPLEX_ CAPABLE RO H 1 1 1000BASE T full duplex capable 0 not 1000BASE T full duplex capable 12 1000BASE_T_...

Page 508: ...ts enabled 11 FORCE_INTERRUPT RW 0 1 force interrupt status to active 0 normal interrupt operation 10 BYPASS_ENCODER RW 0 1 bypass 4B5B encoder and decoder 0 normal operation 9 BYPASS_SCRAMBLER RW 0 1...

Page 509: ...packets 01 support 10k byte packets 00 support 5k byte packets w 200ppm offset MSB is located at expansion reg 46 14 Bit Name R W Default Description 15 AUTONEG_BASE_PG_SELECTOR_FIELD_ MISMATCH RO LH...

Page 510: ...END RO LH 0 1 bad ESD error detected since last read 0 no bad ESD error detected since last read 3 RECEIVE_ERROR_DETECTED RO LH 0 1 receive coding error detected since last read 0 no receive error det...

Page 511: ...with transmit error codes when TXERVIS bit in test register is set Freezes at FFh Counts SerDes errors when register 1ch shadow 11011 bit 9 1 otherwise copper errors Bit Name RW Default Description 15...

Page 512: ...e filter disabled overrides Phy Control and other MII register settings if disabled 0 receiver inv partial response filter enabled 0 5 4 EDGERATE CONTROL 100TX LSB or ed with ER pin RW 00 4 0 ns 100TX...

Page 513: ...ects shadow register zzz to be read Bits 11 3 don t care When bit 15 0 these bits are ignored Bits 2 0 111 This sets the Shadow Register Select to 111 Miscellaneous Control register Read register 18h...

Page 514: ...igdet threshold controlled by bit 7 1 7 10 BASE T SIGNAL DETECT THRESHOLD RW 0 high signal detect threshold 1 low signal detect threshold 0 6 10BT ECHO MODE RW 1 echo transmit data to receive data 0 n...

Page 515: ...NON STOP IP PHONE DETECT MODE RW 1 IP status will always update 0 IP status will halt after detecting an IP PHONE 0 14 10 EXTENDED LINK PULSE WIDTH COUNTER RW 00000 normal link pulse width otherwise a...

Page 516: ...er is an IP PHONE 0 link partner is not an IP PHONE if bit 4 set on read otherwise not determined 0 2 0 SHADOW REGISTER SELECTOR REFERENCE ONLY RW Writes to the selected shadow register are done on a...

Page 517: ...normal operation 0 4 SWAP RXMDIX RW 1 rx and tx operate on same pair 0 normal operation 0 3 HALFOUT RW 1 transmit half amplitude all speeds 0 normal operation also see exp reg f9 1 0 2 0 SHADOW REGIS...

Page 518: ...elect old PCS encoding for PCS receive 0 6 Old PCS Encoding TX RW 0 Select IEEE compliant PCS encoding for PCS receive 1 Select old PCS encoding for PCS receive 0 5 Enable EC as NEXT RW 1 enable 0 dis...

Page 519: ...p required Reads are selected by first writing to register 18h shadow 7 bits 14 12 110 Bit Name RW Description Default 15 WRITE ENABLE BITS 8 3 RW SC 1 write bits 8 3 0 only write bits 14 12 0 14 12 S...

Page 520: ...Bit Name RW Description Default 15 AUTO NEGOTIATION COMPLETE RO 1 auto negotiation complete 0 auto negotiation in progress 0 14 AUTO NEGOTIATION COMPLETE ACK RO LH 1 entered auto neg link good check...

Page 521: ...ete 1 Indicates the manually selected speed and duplex mode when auto negotiation enable 0 Bit Name RW Description Default 15 IP STATUS CHANGE register 1c shadow 5 bit 5 0 RO LH 1 IP status changed si...

Page 522: ...changed since last read 0 interrupt cleared 0 4 LOCAL RECEIVER STATUS CHANGE RO LH 1 local receiver status changed since last read 0 interrupt cleared 0 3 DUPLEX MODE CHANGE RO LH 1 duplex mode chang...

Page 523: ...14 10 to zzzzz The subsequent register read from register 1Ch contains the shadow zzzzz register value PHY 0x1C Shadow 0x1 register read Procedure int value phy_write 0x1C 0x0400 switch to shadow 0x1...

Page 524: ...de 0 normal mode 1 bypass internal yellow and blink clocks 1 enable external yellow and blink clocks via tpin0 and tpin2 respectively 0 use internally generated clocks 0 spare 00000000 Bit Name RW Des...

Page 525: ...gnore on read 0 2 BICOLOR LINK SPEED LED MODE RW 1 enable Bicolor Link Speed led mode LINKSPD 1 0 speed 10 1000 base t 01 100 base t 11 auto negotiation 10 base t 0 1 LOST TOKEN FIX DISABLE RW When 0...

Page 526: ...rx_clk 1011 RGMII rx_clk 1100 TBI RBC0 1101 TBI RBC1 0000 Bit Name RW Description Default 15 WRITE ENABLE RW 1 write bits 9 0 0 read bits 9 0 0 14 10 SHADOW REGISTER SELECTOR RW Shadow Register Select...

Page 527: ...ore enabling clocks and analog components Only applicable when dll is powered down during auto power down r1c 5 bit 1 is LOW 0 8 txc rxc disable during auto power down RW 1 disable txc rxc during auto...

Page 528: ...of 8 ns minimum value 1 001 4 3 TX CHANNEL SEL RW channel to transmit test pulse 00 2 1 RX CHANNEL SEL RW channel to receive test data 00 0 TDR START DONE RW SC write 1 tdr start self clearing read 1...

Page 529: ...low 7 FDXLED_N RO active low 6 INTR_N RO active low 5 SPARE RO ignore on read 4 3 LINKSPD_N RO 11 no link 10 10bt link 01 100tx link 00 1000t link 2 TRANSMIT LED RO active low 1 RECEIVE LED RO active...

Page 530: ...3 below 0 3 ACTIVITY LED ENABLE RW 1 normal operation activity led indicates transmit or receive activity 0 activity led indicates receive activity only 1 2 REMOTE FAULT LED ENABLE RW 1 drive remote...

Page 531: ...frequency locked This will essentially bypass the FIFO with the lowest possible latency in 10 100 speeds useful for applications where the MAC is in RGMII mode and the PHY is in RGMII SGMII slave mode...

Page 532: ...ckplane applications to attach a remote phy to a mac 0 normal operation 00 8 ENABLE REMOTE ACCESS RW 1 Enable remote mac link partner to access local MDIO registers via SerDes autoneg next page MDIO m...

Page 533: ...a when auto negotiation is disabled unless rudi idle detected Force xmit idle if rudi config 0 normal operation 1 1 SERDES AUTO NEGOTIATION PARALLEL DETECT ENABLE RW 1 turn auto negotiation on off in...

Page 534: ...down for 3 seconds before waking up 0 power down for 5 seconds before waking up 0 6 SERDES TRANSMIT DISABLE RW 1 force all SerDes transmit data to 0 0 normal operation 0 5 SIGNAL DETECT ENABLE RW 1 f...

Page 535: ...O 1 signal detect amplitude is above the minimum threshold 0 signal detect amplitude is below the minimum threshold 0 5 SD AMPLITUDE STATUS CHANGED RO LH 1 signal detect amplitude status has changed s...

Page 536: ...force dig1000x speed to copper speed used to test FIFOs in 10 100 mode from GMII pins 0 normal operation 0 8 DLL BYPASS CLOCK ENABLE RW 1 enable dll bypass clock tpin 11 0 disable dll bypass clock 0...

Page 537: ...WENT DOWN FROM LOSS OF SYNC RO LH 1 a valid link went down due to a loss of synchronization for over 10 ms 0 failure condition has not been detected since last read 0 5 IDLE DETECT STATE RO LH 1 idle...

Page 538: ...1 Transmit packet on SerDes pins with txen txer txd 55h for duration of false carrier received on copper pins in SGMII GBIC half duplex mode 0 ignore false carriers in SGMII GBIC mode 1 6 DISABLE CARR...

Page 539: ...ards SerDes MAC RW dig1000x_tx_fifo and dig1000x_rx_fifo FIFO ELASTICITY 1 0 11 support 20k byte packets 10 support 15k byte packets 01 support 10k byte packets 00 support 5k byte packets w 200 ppm of...

Page 540: ...last read 0 page has not been received since last read 0 3 CURRENT OPERATING DUPLEX MODE RO 1 phy is operating in full duplex mode 0 phy is operating in half duplex mode or auto negotiation has not co...

Page 541: ...ast read 0 no false carrier jammed or mode is disabled via register 1ch shadow 1bh 7 0 5 FALSE CARRIER DETECTED RX SIDE RO LH 1 false carrier detected on SerDes receiver since last read 0 no false car...

Page 542: ...ve and link for leds regardless of the mode selected 0 5 QUALIFY FIBER SD WITH SYNC_STATUS 100FX LINK RW 1 fiber signal detect from pin is ANDed with sync_status in 1000 x and link in 100 fx mode Used...

Page 543: ...link up in fiber SGMII or GBIC modes when set in SGMII or GBIC mode then both copper and SerDes link must be valid 0 link down 0 5 COPPER ENERGY DETECT RO 1 copper energy detected 0 no copper energy...

Page 544: ...ter slave seed when bit 11 in reg 1Fh is set and the link partner base page is received writable value is used immediately when bit 9 in reg 1Fh is set 000h RW when writeable link partner ability test...

Page 545: ...HCD 100T Link never came up RO LH 1 100tx half duplex hcd and link never came up occurred since last read 0 hcd cleared 0 1 HCD 10T FDX Link never came up RO LH 1 10base t full duplex hcd and link nev...

Page 546: ...r can t lock within 730us of link or lock loss 0 5 DISABLE POLARITY ENCODE RW 1 disable 1000BASE T polarity encoding 0 normal operation 0 4 ENABLE SOFTWARE TRIM SETTING MAIN DAC RW 1 use software trim...

Page 547: ...R M S SEED RW 1 link partner master slave seed may be overwritten by MII management 0 normal operation 0 7 TRANSMIT 10B MODE RW 1 force GMII transmit into 10B mode 0 use normal mode bit 0 6 RECEIVE 10...

Page 548: ...1 register 11h 0 1000XCONTROL2 1000XControl 2 register 12h 0 1000XCONTROL3 1000XControl 3 register 14h 0 1000XSTATUS1 1000XStatus 1 register 15h 0 1000XSTATUS2 1000XStatus 2 register 16h 0 1000XSTATU...

Page 549: ...Reg 01h MII Status Reg 02h PHY ID MSB Reg 03h PHY ID LSB Reg 04h Auto Neg Advertisement Reg 05h Anto Neg Link Partner Ability Reg 06h Auto Neg Expansion Reg 0Fh IEEE Extended Status Reg IEEE Defined R...

Page 550: ...only This field is ignored in 1000Base X operation 1X 1000 Mbps 01 100 Mbps 00 10 Mbps 0x0 12 AN_EN RW Auto negotiation enable 0 Disable 1 Enable AN 1 11 PWRDN RW Power down GE SerDes 0 Normal operat...

Page 551: ...able 0 10 10BASET2_FDX RO 0 Incapable 1 10BASE T2 full duplex capable 0 9 10BASET2_HDX RO 0 Incapable 1 10BASE T2 half duplex capable 0 8 EXT_STATUS RO 0 No extended status 1 Extended status in regist...

Page 552: ...egister Bits Name RW Description Default 15 10 OUI_MSB RO Bits 3 18 of organizationally unique identifier 101111 9 4 MODEL RO Device Model number 111111 3 0 REVISION RO Device revision number 0000 Tab...

Page 553: ...4 ACK RO 0 Link partner has not received link code word 1 Link partner has received link code word 0 13 12 RF RO Remote fault 2 b00 No fault 2 b01 Link failure 2 b10 Offline 2 b11 Auto negotiation err...

Page 554: ...ved 0x000 2 NP_ABILITY RO Next page ability 0 Local device is not next page capable 1 Local device is next page capable 0 1 PG_REC RO Page received 0 New link code word has not been received 1 Receive...

Page 555: ...1 SEL_RX_PKTS_FOR_ CNTS RW 0 Select CRC errors for 0 17h counter 1 Select received packets for 0 17h counter 0 10 REMOTE_LOOPBACK RW 0 Normal operation 1 Enable remote loopback operates in 10 100 1000...

Page 556: ...TERFACE RW 0 GMII interface 1 Ten bit interface 1 0 FIBER_MODE_1000X RW 0 SGMII mode 1 Fiber mode 1000X 1 Table 135 1000XCONTROL2 Bits Name RW Description Default 15 DIS_EXTEND_FDX RW 0 Normal operati...

Page 557: ...or 0 3 ENABLE_AUTONEG_ ERR_TIMER RW 0 Normal operation 1 Enable auto negotiation error timer Error occurs when timer expires in ability detect ack detect or idle detect When the error occurs config wo...

Page 558: ...11 EXT_PHY_CRS_MODE RW 0 Normal operation 1 Use external pin for the PHYs receive only crs output Useful in SGMII 10 100 half duplex applications in order to reduce the collision domain latency Requi...

Page 559: ...t necessary if MAC uses crs to determine collision 0 3 EARLY_PREAMBLE_TX RW 0 Normal operation 1 Send extra bytes of preamble to avoid FIFO latency Used in half duplex applications to reduce collision...

Page 560: ...fsm 0 No carrier extend error since last read 0 8 EARLY_END_EXT_DE TECTED RO 1 Early end extension since last read early_end_ext in pcs receive fsm 0 No early end extension since last read 0 7 LINK_ST...

Page 561: ...since last read 0 12 SGMII_SELECTOR_MI SMATCH RO 1 SGMII selector mismatch detected since last read auto negotiation page received from link partner with bit 0 0 while local device is in SGMII mode 0...

Page 562: ...is powered down from register 0 11 This status signal is the signal detect input port when register 0 10h bit 3 is 0 otherwise it is the signal detect input port inverted 0 7 SD_FILTER_CHG RO 1 Signa...

Page 563: ...use if fiber auto power down is enabled register 2 10h 12 0 31 42 ms 0 9 6 FX100_RXDATA_SEL RW Selects the sample bit out of 10 bits for FX100 RX data 0x9 5 FX100_DISABLE_RX_QUAL RW 1 Always use samp...

Page 564: ...alignment in 100FX mode 0 Normal operation 0 3 FX100_FORCE_LINK RW 1 Force link in 100FX mode 0 Normal operation 0 2 FX100_FORCE_LOCK RW 1 Force lock in 100FX mode 0 Normal operation 0 1 FX100_FAST_U...

Page 565: ...o lock within 730us since last read 0 Condition not detected since last read 0 3 FX100_LOST_LOCK RO LH 1 Lost lock since last read 0 Lock has not been lost since last read 0 2 FX100_FAULTING RO LH 1 F...

Page 566: ...the data to the device and the data is looped back to the wire at the analog block prior of reaching to the de serializer The data will not reach the device MAC block In order to use the remote loopb...

Page 567: ...boost 0 13 10 RESERVED RW Reserved 0x0 9 BMODE RW Reserved for factory use only 1 Enable transmit boost mode 0 Normal operation 0 8 5 PREDRIVER_CURRE NT RW This is to control the output driving ampli...

Page 568: ...sed on energy level 000 10 mV 001 20 mV 011 30 mV 010 40 mV 110 50 mV 111 60 mV 101 70 mV 100 80 mV 0x2 9 SIGDET_EN RW 1 Enable signal detect 0 Disable signal detect 0 8 LOOPBACK RW Set to enable remo...

Page 569: ...n Controlling the GE PLL circuitry Register Offset 0x18 at Block 3 Table 148 ANALOG_RX2 Bits Name RW Description Defaul t 15 4 RESERVED RW Reserved 0x000 3 100FX_ENABLE RW Set to enable SerDes in 100...

Page 570: ...E_prbs_status Bit Name RW Description Default 15 4 Reserved RO Reserved 0x0 3 2 Prbs_order RW 0 7th order 1 15th order 2 23rd order 3 31st order 0 1 Inv_prbs_order RW Set to invert the polynomial orde...

Page 571: ...45 DEV 7 Reg803Eh the following register sequence may be followed Write bits 15 14 to 00 to register 0Dh to set the function field to Address and set bits 4 0 to 00111 to set DEVAD to 7 Write 803Eh t...

Page 572: ...EEE Resolution Status Table 152 Clause 45 Register Dev 3 Reg14h EEE Capability Register Bit Name RW Description Default 15 3 Reserved RO Ignore on read 0 2 1000BASE T EEE RO 1 EEE is supported for 100...

Page 573: ...de Clause 45 Register Dev 7 Reg803dh 32817d EEE Control Register LPI Feature Enable Setting this bit high enables LPI 2 EEE 1000BASE T Resolution RW 1 Both local device and link partner advertise EEE...

Page 574: ...or PAUSE MAC control functions MAC control layers will provide two indicators paused and not paused The Enet source address equals the unicast address of the MAC sublayer which transmits the pause_fra...

Page 575: ...s Speed Mismatch The Client sends pause frame s to the switch see Figure 57 The Client s pipe has been saturated and the RX buffers are almost exhausted The Client begins sending pause frames when the...

Page 576: ...buffers some packets but eventually hits an internal threshold memory will run short Since dropping packets is undesirable the switch must slow incoming packets from the server The duplex mode of the...

Page 577: ...ent by the Gigabit Client Figure 59 File Transfer Scenario Switch Backpressure Switch Flow Control The Switch can only use IEEE 802 3x flow control when the link is configured for full duplex operatio...

Page 578: ...Figure 62 MAC control frames must pad zeros into the unused portion of the payload A flow control frame contains the following fields Destination address field set to 01 80 C2 00 00 01 Source address...

Page 579: ...ce RX Return Ring Interrupt Service Routine ISR A procedure where device interrupts are processed Pre boot execution PXE An industry standard client server interface that allows networked computers th...

Page 580: ...1000210 0x0100021F 0x00000210 0x0000021F 0x00000210 0x0000021F Receive Return Ring2 RCB 16B 0x00000220 0x0000022F 0x01000220 0x0100022F 0x00000220 0x0000022F 0x00000220 0x0000022F Receive Return Ring3...

Page 581: ...B 0x40000000 0x400004FF PCI Configuration 256B 0xC0000000 0xC00000FF 0x00000000 0x000000FF 0x00000000 0x000000FF 0x00000000 0x000000FF High Priority Mailbox 512B 0x00000200 0x000003FF 0x00000200 0x000...

Page 582: ...6 5718 PG108 R Page 582 Receive Jumbo Producer RCB0 NIC Address 4B 0x00044400 0x0004440F 0x01044400 0x0104440F 0x00044400 0x0004440F 0x00044400 0x0004440F Table 157 BCM5717 BCM5718 Memory Map Cont Reg...

Page 583: ...FFF Unused SDC 0x1000 0x13FF 0x1000 0x100B Send data Completion 0x100C 0x13FF Unused SBDS 0x1400 0x17FF 0x1400 0x147F SBDS Registers 0x1480 0x17FF Unused SBDI 0x1800 0x1BFF 0x1800 0x1847 Send BD Initi...

Page 584: ...Low Priority Mail Box 0x5903 0x5BFF Unused FTQ 0x5C00 0x5FFF 0x5C00 0x5CFF Flow Through Queue 0x5D00 0x5FFF Unused MSI 0x6000 0x63FF 0x6000 0x6007 Message Signaled Interrupt 0x6008 0x63FF Unused CFG P...

Page 585: ...x00000230 0x0000023F VRQ Receive Return Ring RCBs 4 16 208B 0x00000240 0x0000030F 0x01000240 0x0100030F 0x00000240 0x0000030F 0x00000240 0x0000030F Unmapped 2 3KB 0x00000420 0x00000B4F 0x01000420 0x01...

Page 586: ...d 28KB 0xC0030000 0xC0036FFF 0xC0030000 0xC0036FFF 0xC0030000 0xC0036FFF 0xC0030000 0xC0036FFF Unmapped 4KB 0xC0037000 0xC0037FFF 0xC0037000 0xC0037FFF 0xC0037000 0xC0037FFF 0xC0037000 0xC0037FFF RXCP...

Page 587: ...0x1000 0x13FF 0x1000 0x100B Send data Completion 0x100C 0x13FF Unused SBDS 0x1400 0x17FF 0x1400 0x147F SBDS Registers 0x1480 0x17FF Unused SBDI 0x1800 0x1BFF 0x1800 0x1847 Send BD Initiator 0x1848 0x...

Page 588: ...Low Priority Mail Box 0x5903 0x5BFF Unused FTQ 0x5C00 0x5FFF 0x5C00 0x5CFF Flow Through Queue 0x5D00 0x5FFF Unused MSI 0x6000 0x63FF 0x6000 0x6007 Message Signaled Interrupt 0x6008 0x63FF Unused CFG P...

Page 589: ...g3 RCB 16B 0x00000230 0x0000023F 0x01000230 0x0100023F 0x00000230 0x0000023F 0x00000230 0x0000023F VRQ Receive Return Ring RCBs 4 16 208B 0x00000240 0x0000030F 0x01000240 0x0100030F 0x00000240 0x00000...

Page 590: ...cratch Pad 28KB 0xC0030000 0xC0036FFF 0xC0030000 0xC0036FFF 0xC0030000 0xC0036FFF 0xC0030000 0xC0036FFF Unmapped 4KB 0xC0037000 0xC0037FFF 0xC0037000 0xC0037FFF 0xC0037000 0xC0037FFF 0xC0037000 0xC003...

Page 591: ...000 0x23FF 0x2000 0x2258 Receive List Placement 0x2259 0x23FF Unused RDI 0x2400 0x27FF 0x2400 0x24C3 Receive Data Initiator 0x24C4 0x24FF Unused 0x2500 0x27FF VRQ RCB Registers RDC 0x2800 0x2BFF 0x280...

Page 592: ...F Unused MSI 0x6000 0x63FF 0x6000 0x6007 Message Signaled Interrupt 0x6008 0x63FF Unused CFG Port 0x6400 0x67FF 0x6400 0x67FF PCIe Core Private Registers Access to Configuration Space GRC 0x6800 0x6BF...

Page 593: ...thout further notice to any products or data herein to improve reliability function or design Information furnished by Broadcom Corporation is believed to be accurate and reliable However Broadcom Cor...

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