2/24/2008 9T6WP
BCM7405
Preliminary Hardware Data Module
Functional Description
06/29/07
Bro a d c o m C o rp o r a ti o n
Page 1-92
Testability
Document
7405-1HDM00-R
T
ESTABILITY
O
VERVIEW
The BCM7405 uses a combination of production, functional and on-board tests.
P
RODUCTION
T
ESTING
Scan
Scan logic is inserted and ATPG vectors are created that exercise the scan chains.
Built-In Self-Test
Internal SRAM modules are examined by a Built-In Self-Test (BIST) sequence. Multiple SRAM cores can be tested with the
same BIST controller.
F
UNCTIONAL
T
ESTING
Test Modes
Each major module has a suite of test to prove their functionality in test modes. These tests can be self-checking or they are
compared to golden test patterns.
Test Buses
During Test mode, the core under test has various internal signals routed to external pins to improve internal visibility. In
addition, input test bus is used to accommodate the test input signals. Both input and output test buses are mapped to
various pins of the chip by internal test multiplexing logic.
O
N
-B
OARD
T
ESTING
JTAG
Manufacturing correctness is verified using a JTAG option. This ensures physical connectivity from the board to the chip.
EJTAG
For processor bring-up and verification, EJTAG is used to probe the on-chip processor. The EJTAG standard allows the
following features:
•
Software Debug Breakpoint Instruction (SDBBP)
•
Hardware breakpoints—four instruction and two data break points
•
Single-step operations
