16
JP17 : WDT Time - Out Period
PERIOD
1-2
3-4
5-6
7-8
*1 sec
OFF
OFF
ON
OFF
2 sec
OFF
OFF
ON
ON
10 sec
OFF
ON
OFF
OFF
20 sec
OFF
ON
OFF
ON
110 sec
ON
OFF
OFF
OFF
220 sec
ON
OFF
OFF
ON
The Watch-dog timer is disabled after the system Power-On. The
watch-dog timer can be enabled by a Enable cycle with reading the
control port (443H), a Refresh cycle with reading the control port (443H)
and a Disable cycle by reading the Watch-dog timer disable control port
(043H). After a Enable cycle of WDT, user must constantly proceed a
Refresh cycle to WDT before its period setting comes ending of every 1,
2, 10, 20, 110 or 120 seconds. If the Refresh cycle does not active
before WDT period cycle, the on board WDT architecture will issue a
Reset or NMI cycle to the system.
The Watch-Dog Timer is controlled by two I/O ports.
443H
I/O Read The Enable cycle.
443H
I/O Read The Refresh cycle.
043H
I/O Read
The Disable cycle.
The following sample programs showing how to Enable, Disable and
Refresh the Watch-dog timer:
WDT_EN_RF
EQU
0443H
WDT_DIS
EQU 0043H
WT_Enable
PUSH
AX
; keep AX DX
PUSH
DX
MOV
DX,WDT_EN_RF ; enable the watch-dog timer
IN
AL,DX
POP
DX
; get back AX, DX
POP
AX
RET