Boonton 1121A, Instruction Manual

Page: 60 / 181

Section 4 Theory of Operation
4-14
4-73. A quadrature detector is formed by U1 and associ-
ated components. The output of U1 is a TTL compatible
square wave used in the ALC loop to detect the peak of
the source output waveform. The output of U1 is buffered
by gate U6a and is used to generate the rear panel SYNC
output (TP8). The SOFRQ output is also applied to the
counter circuits to enable internal measurement of the
actual source frequency.
4-74.
The source output signal is AC coupled by C1 and
R1 and applied to a track-and-hold circuit, U9. The
quadrature detector generates the track and hold control
signal which tracks the rise of the sinusoid and holds the
peak value for 180 degrees. The output of U9 (TP4) is
sampled by U10 immediately following the start of the
hold period. The hold period of U9 effectively extends the
peak of the sinusoid to eliminate sampling aperture
errors. The 30 µs sampler aperture is determined by
one-shot U5a and timing network C6 and R16. The output
of U10 (TP5) is a DC level equal to the positive peak
amplitude of the source output signal. Voltage reference
U7 gen5 volts which is applied to a voltage divider
network formed by R5, R23, and R12. Oscillator
calibration adjustment R23 allows fine adjustment of the
source output level. The output of U10 is subtracted from
the calibration reference by amplifier U2b and associated
components forming an error voltage. Error integrator U3
is enabled by shunt chopper Q1 (TP6) during the 30 µs
sampling period. A level translator circuit consisting of U4
and associated components convert the TTL sampling
signal to gate drive levels to control FET Q1. The output
of the error integrator, U3, is amplified by U2a and applied
to four-quadrant multiplier U10 to complete the ALC
control loop. One-shot U5b and timing network R17 and
C7 forms a start-up circuit which triggers after a 200 ms
absence of the quadrature signal. When U5b triggers, U9
and U10 are set in track and sample modes to guarantee
oscillation when the power is first applied and when there
is no quadrature signal.
4-75.
The fine tune and ALC error voltages are applied to
four-quadrant multipliers U10 and U18. The current
outputs through pin 4 of each multiplier is summed to-
gether and amplified by U11a. The output of U11a is the
product of the ALC error and fine tune voltages and the
in-phase (TP1) and quadrature (TP2) signals which are
summed back into the oscillator through U12a. The ALC
control loop can be disabled to aid in troubleshooting the
oscillator circuits by removing U10. In this design the ALC
control loop operates to reduce oscillation, therefore,
removing U10 causes the oscillator level to increase to
the limit set by the limiter circuits controlling U12b. The
oscillator and ALC circuits can then be investigated
individually.
4-76. A7 Output Circuits.
The output circuits consist of
the differential power output amplifier (located on the rear
panel heat sink), the variable gain and attenuation to
cover a level range of 0.01 mV to 16 volts, and the
programmable DC voltage used to fine tune the
frequency of the source circuits. Refer to Figure 4-10.
4-77.
The source oscillator output is applied to resistors
R13 through R32. The values of these resistors are
chosen in a binary series to operate as a discrete 12 bit
D/A converter. These resistors are selected for level
increments within the 16 volts, 3 volt, 300 mV or 30 mV
level ranges by FET switches Q3 through Q14. The three
most significant bits are trimmed for maximum accuracy
by resistor R15, R17, and R21. Data from the control
program is latched in data latches U4 and U5. The 14
comparators contained in U6 through U9 and associated
pull-up resistors R4, R5, and R6 act as level translators to
convey the latched TTL data to gate drive levels
necessary to operate the FET switches. Amplifier U10 is a
summing amplifier which combines the currents from the
selected bits in the discrete 12 bit D/A converter. Analog
switch U11 and resistors R9 and R36 form a
programmable attenuator with selections of 0 dB, -20 dB
and OFF. The -20 dB range is enabled for signal levels of
30.00 mV and below. In the signal-to-noise measurement
mode, U11 is configured to squelch the source output
during the noise measurement interval.
4-78.
The output amplifier is formed by rear panel
assembly A24. The single-ended signal is applied to
amplifiers U1 and U2 to form a differential HI and LOW
output. The LOW amplifier formed by U1, Q4, Q6 and
associated circuitry is configured as an inventing amplifier
while U2, Q7, Q10 and associated circuitry is non
inverting and drives the HI output. The power transistors
Q4, Q6, Q7, and Q10 are current boosters to supply
current into impedances as low as 50 ohms.
4-79.
The fine tune voltage is generated by 12 bit D/A
converter U1. A 10 volt reference for the D/A converter
(TP1) is provided by U3. Amplifier U2a provides a 0 to -10
volt output from the D/A converter while U2b and resistors
R1, R2, and R3 generate a -6.7 to +13.4 volt output range
to tune the source oscillator (TP3).