21
APPENDIX B: Block Diagram
Appendix B: Block Diagram
6
4
8
20
5
3
2
7
SERIAL
INTERF
ACE
DCE/DTE
DETECT
OR
CONTROL
2
3
4
5
6
7
8
9
P
ARALLEL
INTERF
ACE
CENTRONICS
CONNECT
OR
1
10
11
12
13
16
DA
T
A
BIT 1
DA
T
A
BIT 2
DA
T
A
BIT 3
DA
T
A
BIT 4
DA
T
A
BIT 5
DA
T
A
BIT 6
DA
T
A
BIT 7
DA
T
A
BIT 8
STROBE
ACKNOWLEDGE
BUSY
P
APER END
SELECT
ERROR
GROUND
DSR
RTS
DCD
DTR
CTS
RD
TD
GND
P
ARALLEL
AND
SERIAL
PROCESSOR
REGULA
T
OR
WITH
RESET
MONIT
O
R
RESET
DIP
SWITCH
SETTINGS FOR
RA
TE/LENGTH/P
ARITY
POWER
SUPPL
Y
6
4
8
20
5
3
2
7
DSR
RTS
DCD
DTR
CTS
RD
TD
GND
9
+VIN
+V
-V
+5V
DB-25
CONNECT
OR
EXTERNAL
POWER JACK
