TA785GE/TA785GE 128M BIOS Manual
35
DRAM Timing Configuration
BIOS S ETUP UTILITY
vxx.xx (C)C opyright 198 5-200x, Amer ican Megatre nds, Inc.
S elect Screen
S elect Item
G o to Sub Scr een
G eneral Help
S ave and Exit
E xit
En ter
F1
F1 0
ES C
DRAM Timing Config uration
Mem ory CLK
CAS Latency(Tcl)
RAS /CAS Delay(Tr cd)
Row Precharge Ti me(Trp)
Min Active RAS(T ras)
RAS /RAS Delay(Tr rd)
Row Cycle (Trc)
Com mand Rate(CR)
Wri te Recover Ti me(Twr)
> Memory Configuratio n
> ECC Configuratio n
Memor y Clock Mode [ Auto]
DRAM Timing Mode [ Auto]
T-Series
M emory Configuration
BIOS S ETUP UTILITY
vxx.xx (C)C opyright 198 5-200x, Amer ican Megatre nds, Inc.
S elect Screen
S elect Item
C hange Option
G eneral Help
S ave and Exit
E xit
+-
F1
F1 0
ES C
Memor y Configurati on
Bank Interleaving [ Auto]
Chann el Interleavi ng [ XOR of Addre ss bit]
Enabl e Clock to Al l DIMMs [ Disabled]
MemCl k Tristate C3 /ATLVID [ Disabled]
Memor y Hole Remapp ing [ Enabled]
DCT U nganged Mode [ Always]
Power Down Enable [ Disabled]
Enab le Bank Memo ry
Inte rleaving
T-Series
Bank Interleaving
Bank Interleaving is an advanced chipset technique used to improve memory
perform ance. Memory interleaving increases bandwidth by allowing simultaneous
access to more than one piece of memory.
Options: Auto (Default) / Disabled
