51
Note: Because the overclock, overvoltage, and hardware monitor
features are controlled by several separate chipset,
[ WarpSpeeder™ ] divide these features to separate panels. If one
chipset is not on board, the correlative button in Main panel will be
disabled, but will not interfere other panels’ functions. This property
can make [ WarpSpeeder™ ] utility more robust.
Summary of Contents for P4TDH
Page 36: ...33 CPU 1 90 2 A CPU A CPU 3 CPU JCFAN1 CPU JCFAN1 JSFAN1 CPU JCFAN1 1 12V JSFAN1 12V 1...
Page 42: ...39 JAUDIO1 JCDIN1 1 2 JAUDIO1 1 JCDIN1 C D R O M...
Page 53: ...50...
Page 58: ...55 DIMM CD ROM CMOS CD ROM Invalid Configuration CMOS Failure...
Page 59: ...56 2 SETUP...
Page 60: ...57 07 22 2002...