NF720D A2G+ BIOS M anual
28
DRAM Timing Configuration
BIOS SETU P U TILITY
vxx .xx (C)Copyright 1985-200x, American Me gatrends, Inc.
S elect Screen
S elect Item
G o to Sub Screen
G eneral Help
S ave and Exit
E xit
Enter
F1
F10
ESC
DRAM Timing Co nfiguration
Memory CLK
CAS Latency( Tcl)
RAS/CAS Dela y(Trcd)
Row Precharg e Time(Trp)
Min Active R AS(Tras)
RAS/RAS Dela y(Trrd)
Row Cycle (T rc)
Command Rate (CR)
> Memory Confi guration
DRAM Timing Mo de [Aut o]
Performance
M emory Configuration
BIOS SETU P U TILITY
vxx .xx (C)Copyright 1985-200x, American Me gatrends, Inc.
S elect Screen
S elect Item
C hange Option
G eneral Help
S ave and Exit
E xit
+-
F1
F10
ESC
Memory Configu ration
Bank Interleav ing [Aut o]
Channel Interl eaving [XOR of Address bit]
Enable Clock t o All DIMMs [Dis abled]
MemClk Tristat e C3/ATLVID [Dis abled]
Memory Hole Re mapping [Ena bled]
DCT Unganged M ode [Alw ays]
Power Down Ena ble [Dis abled]
Enable Bank Memory
Interleaving
Performance
Bank Interleaving
Bank Interleaving is an advanced chipset technique used to improve memory
perform ance. Memory interleaving increases bandwidth by allowing simultaneous
access to more than one piece of memory.
Options:
Auto (Default) / Disabled
