BIOS
CB6464
56
Version: 0.4
9.33
PCI Express Configuration
Bios-Entry
Options
PCI Express Configuration
PCI Express Clock Gating
Disabled / Enabled
Lagacy IO Low Latency
Disabled / Enabled
Peer Memory Write Enable
Disabled / Enabled
Compliance Test Mode
Disabled / Enabled
PCIe-USB Glitch W/A
Disabled / Enabled
PCI Express Gen3 Eq Lanes
PCI Express Root Port X
[PCIE Port assignments]
None
9.34
PCI Express Gen3 Eq Lanes
Bios-Entry
Options
PCIEX Cm
0..63
PCIEX Cp
0..63
Summary of Contents for CB6464
Page 1: ...Manual for Computerboard CB6464 0 4 25 10 2019 Version Date...
Page 2: ......
Page 6: ...CB6464 6 Version 0 4...
Page 64: ...Mechanical drawings CB6464 64 Version 0 4 10 2 PCB Pin 1 distances Fig 14 MZ Pin1 CB6464_G3...
Page 65: ...Mechanical drawings CB6464 65 Version 0 4 10 3 PCB Dimensions Fig 15 MZ CB6464_G3...