BLOCK DIAGRAM
STATE
C O N T R O L
W E #
C E #
OE#
BYTE#
C O M M A N D
R E G I S T E R
DQ[15:0]
A[18:0], A-1
V
C C
D E T E C T O R
T I M E R
E R A S E V O L T A G E
G E N E R A T O R A N D
S E C T O R S W I T C H E S
P R O G R A M
V O L T A G E
G E N E R A T O R
ADDRESS LATCH
X - D E C O D E R
Y - D E C O D E R
8 Mb FLASH
M E M O R Y
A R R A Y
Y-GATING
D A T A L A T C H
I/O BUFFERS
I/O CONTROL
R E S E T #
DQ[15:0]
A[18:0], A-1
RY/BY#
36
Summary of Contents for DV913S
Page 1: ...SERVICE MANUAL DV913S...
Page 12: ...7 MPEG BOARD CHECK WAVEFORM 7 1 27MHz WAVEFORM DIAGRAM 7 2 ICVIPER22 PIN 5 WAVEFORM DIAGRAM 10...
Page 42: ...FRONT SCHEMATIC DIAGRAM 40 9 SCHEMATIC PCB WIRING DIAGRAM...
Page 44: ...POWER BOARD SCHEMATIC DIAGRAM 42...
Page 46: ...MIAN SCHEMATIC DIAGRAM 44...
Page 51: ...49...
