KEY FEATURES
n
5 Volt Read, Program, and Erase
– Minimizes system-level power requirements
n
High Performance
– Access times as fast as 55 ns
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Low Power Consumption
– 20 mA typical active read current in byte
mode, 28 mA typical in word mode
– 35 mA typical program/erase current
– 5 µA maximum CMOS standby current
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Compatible with JEDEC Standards
– Package, pinout and command-set
compatible with the single-supply Flash
device standard
– Provides superior inadvertent write
protection
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Sector Erase Architecture
– Boot sector architecture with top and
bottom boot block options available
– One 16 Kbyte, two 8 Kbyte, one 32 Kbyte
and fifteen 64 Kbyte sectors in byte mode
– One 8 Kword, two 4 Kword, one 16 Kword
and fifteen 32 Kword sectors in word mode
– A command can erase any combination of
sectors
– Supports full chip erase
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Erase Suspend/Resume
– Temporarily suspends a sector erase
operation to allow data to be read from, or
programmed into, any sector not being
erased
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Sector Protection
– Any combination of sectors may be
locked to prevent program or erase
operations within those sectors
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Temporary Sector Unprotect
– Allows changes in locked sectors
(requires high voltage on RESET# pin)
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Internal Erase Algorithm
– Automatically erases a sector, any
combination of sectors, or the entire chip
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Internal Programming Algorithm
– Automatically programs and verifies data
at a specified address
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Fast Program and Erase Times
– Byte programming time: 7 µs typical
– Sector erase time: 1.0 sec typical
– Chip erase time: 19 sec typical
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Data# Polling and Toggle Status Bits
– Provide software confirmation of
completion of program or erase
operations
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Ready/Busy# Output (RY/BY#)
– Provides hardware confirmation of
completion of program and erase
operations
n
Minimum 100,000 Program/Erase Cycles
n
Space Efficient Packaging
– Available in industry-standard 44-pin
PSOP and 48-pin TSOP and reverse
TSOP packages
A[18:0]
19
C E #
O E #
R E S E T #
B Y T E #
W E #
8
7
DQ[7:0]
DQ[14:8]
DQ[15]/A-1
R Y / B Y #
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