ESS Technology, Inc.
SAM0357-070600
ES4428/ES4427 DATA SHEET
PRELIMINARY
MUTE
15
O
Audio mute output.
MCLK
17
I
Audio master clock input.
AUX0[7]
18
I/O
Auxiliary bus 0.
TWS
19
I
Dual-purpose pin TWS is the transmit audio frame sync input from ES4428.
SPLL_OUT
O
SPLL_OUT is the select PLL output.
AUX1[0]
20
I/O
Auxiliary bus 1.
TSD
21
I
Transmit audio data output from ES4428.
TBCK
22
I
Transmit audio bit clock output from ES4428.
RWS
23
O
Dual-purpose pin RWS is the receive audio frame sync input to ES4428.
SEL_PLL1
I
Pins SEL_PLL[1:0] select the PLL clock frequency for the DCLK output.
RSTOUT#
24
O
Reset output (active-low) to ES4428.
RSD
33
O
Dual-purpose pin. RSD is the receive audio data input to ES4428.
SEL_PLL0
I
SEL_PLL0 along with SEL_PLL1 select the PLL clock frequency for the DCLK
output. See the table for pin number 23.
AUX1[2]
34
I/O
Auxiliary bus 1.
AUX1[3]
35
I/O
Auxiliary bus 1. Interrupt output to ES4428
AUX1[4]
36
I/O
Auxiliary bus 1.
RBCK
37
O
Dual-purpose pin. RBCK is the receive audio bit clock input to ES4428.
SER_IN
I
SER_IN is the serial input DSC mode.
0 - Parallel DSC mode.
1 - Serial DSC mode.
AUX1[5]
38
I/O
Auxiliary bus 1.
AUX1[6]
39
I/O
Interrupt input to modem subsystem.
AUX1[7]
40
I/O
Auxiliary bus 1.
IR
I
IR interrupt input.
VSSAA
41, 51
I
Audio Analog Ground.
VCM
42
I
ADC Common Mode Reference (CMR) buffer output. CMR is approximately 2.25
V. Bypass to analog ground with 47
µ
F electrolytic in parallel with 0.1
µ
F.
VREFP
43
I
DAC and ADC maximum reference. Bypass to VCMR with 10
µ
F in parallel with 0.1
µ
F.
VCCAA
44
I
Analog VCC, 5 V.
AOR+, AOR-
45, 46
O
Right channel output. Differential output.
AOL-, AOL+
47, 48
O
Left channel output. Differential output.
MIC2
49
I
Microphone input 2.
MIC1
50
I
Microphone input 1.
VREFM
53
I
DAC and ADC minimum reference. Bypass to VCMR with 10
µ
F in parallel with
0.1
µ
F.
VSSAV
56, 57,62, 63
I
Video Analog Ground
VCCAV
59, 60
I
Video VCC, 5 V
ACAP
65
I
Audio CAP
AUX[0]6
67
I/O
General purpose I/O.
AUX[0]5
68
I/O
General purpose I/O.
AUX[0]4
69
I/O
Modem DSP reset.
AUX[0]3
70
I/O
CD loader reset.
XOUT
71
O
27 MHz crystal output.
XIN
74
I
27 MHz crystal input.
PCLKX2
80
I
Pixel clock input from host processor, ES4428 PLL and pixel clock synthesizers and
from external video encoder.
Name
Number
I/O
Definition
SEL_PLL1
SEL_PLL0
DCLK
0
0
Bypass PLL (input mode)
0
1
27 MHz (output mode) Default
1
0
32.4 MHz (output mode)
1
1
40.5 MHz (output mode)