Basler racer, Manual, Page: 25 / 46

AW00118702000 Camera Link Implementation
Basler racer Camera Link 19
* In 1X8 8 bit mode, this port is FVAL and is not used.
In 1X8 10 bit mode, FVAL is not present. Instead, this port is I2 and D1 Bit 0 is assigned to it.
** In 1X8 8 bit mode, this port is DVAL.
In 1X8 10 bit mode, DVAL is not present. Instead, this port is I3 and D1 Bit 1 is assigned to it.
Medium/Full SDR Conn, Transmitter Circuit Y
Port Camera Frame
Grabber
Bit Assignments
1X8 - 8 Bits 1X8 - 10 Bits
Port D0 TxIn0 RxOut0 D3 Bit 0 D3 Bit 2
Port D1 TxIn1 RxOut1 D3 Bit 1 D3 Bit 3
Port D2 TxIn2 RxOut2 D3 Bit 2 D3 Bit 4
Port D3 TxIn3 RxOut3 D3 Bit 3 D3 Bit 5
Port D4 TxIn4 RxOut4 D3 Bit 4 D3 Bit 6
Port D5 TxIn6 RxOut6 D3 Bit 5 D3 Bit 7
Port D6 TxIn27 RxOut27 D3 Bit 6 D3 Bit 8
Port D7 TxIn5 RxOut5 D3 Bit 7 (MSB) D3 Bit 9 (MSB)
Port E0 TxIn7 RxOut7 D4 Bit 0 D4 Bit 2
Port E1 TxIn8 RxOut8 D4 Bit 1 D4 Bit 3
Port E2 TxIn9 RxOut9 D4 Bit 2 D4 Bit 4
Port E3 TxIn12 RxOut12 D4 Bit 3 D4 Bit 5
Port E4 TxIn13 RxOut13 D4 Bit 4 D4 Bit 6
Port E5 TxIn14 RxOut14 D4 Bit 5 D4 Bit 7
Port E6 TxIn10 RxOut10 D4 Bit 6 D4 Bit 8
Port E7 TxIn11 RxOut11 D4 Bit 7 (MSB) D4 Bit 9 (MSB)
Port F0 TxIn15 RxOut15 D5 Bit 0 D5 Bit 2
Port F1 TxIn18 RxOut18 D5 Bit 1 D5 Bit 3
Port F2 TxIn19 RxOut19 D5 Bit 2 D5 Bit 4
Port F3 TxIn20 RxOut20 D5 Bit 3 D5 Bit 5
Port F4 TxIn21 RxOut21 D5 Bit 4 D3 Bit 6
Port F5 TxIn22 RxOut22 D5 Bit 5 D3 Bit 7
Port F6 TxIn16 RxOut16 D5 Bit 6 D5 Bit 8
Port F7 TxIn17 RxOut17 D5 Bit 7 (MSB) D5 Bit 9 (MSB)
LVAL TxIn24 RxOut24 Line Valid Line Valid
FVAL or
Port I2 *
TxIn25 RxOut25 Not Used
D1 Bit 0
DVAL or
Port I3 **
TxIn26 RxOut26 Not Used
D1 Bit 1
Port I4 TxIn23 RxOut23 Not Used D2 Bit 0
Strobe TxInCLK RxOutClk Pixel Clock Pixel Clock
Table 9: Bit Assignments for 1X8 Tap Geometry – 8 or 10 Bit Pixel Depth (Transmitter Circuit Y)