PT-5IH
SYSTEM BOARD
HARDWARE SETUP
4. HARDWARE SETUP
4.1
UNPACKING
The system board package should contain the following parts :
The PT-5IH system board.
OPERATION MANUAL.
Cable set for IDE and I/O device.
4.2
HARDWARE CONFIGURATION
Before the system board is ready to operate, the hardware must be configured to allow for various functions
within the system. To configure the PT-5IH system board is a simple task, only a few jumpers, connectors,
cables and sockets needs to be selected and installed. For the detailed locations of each component please refer
to the system board layout figure which appears in page 3-1.
4.2.1 DRAM INSTALLATION
The PT-5IH system board will support two banks main memory (bank0 and bank 1) on board, (using four 72-
Pin SIMM socket, SIMM 1 - 4), each bank could be single or double sided. With the use of 1MB
x
36(32)-S,
2MB
x
36(32)-D, 4MB
x
36(32)-S or 8MB
x
36(32)-D and 16MB
x
36(32)-S SIMM modules, 8MB up to 256 MB of
local memory can be attained. Both standard fast page mode (FPM) and Extended Data Out (EDO) memory are
supported, but they cannot be mixed within the same memory bank. The speed of FPM DRAMs must be used
70ns or faster than 70ns and the speed of EDO DRAMs must be used 60ns or faster than 60ns.
(
Note : S = Single sided
, D = Double sided)
There is no jumper needed for DRAM configuration, DRAMs' type and size will be detected by system BIOS
automatically.
In DRAM memory subsystem, ECC and Parity can be checked on the DRAM interface (selected by BIOS via
CMOS setup, please refer to Chapter 5). The defult status is parity selected. The DRAM SIMMs must be
populated with 72-bit wide memory (with parity bit) to implement ECC or Parity functions.
ECC is an optional data integrity feature provided by the system. This feature provides single-error correction,
double-error detection, and detection of all errors confined to single nibble for DRAM memory subsystem.
4-1
