The KM266-MNB Mainboard
Page 31
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PCI1/PCI2 Master 0 WS Write
When enabled, writes to the PCI 1/PCI 2 bus are executed with zero wait
states.
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PCI1/PCI2 Post Write
You can Enable or Disable the chipset's ability to use a buffer for posted
writes initiated on the PCI 1/PCI 2 bus.
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PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1.
Memory Hole
You can reserve this area of system memory for ISA adapter ROM. When this
area is reserved, it cannot be cached. The user information of peripherals that
need to use this area of system memory usually discusses their memory re-
quirements.
System BIOS Cacheable
Selecting “Enabled” allows caching of the system BIOS ROM. This results
system performance. However, if any program writes to this memory area, a
system error may occur.
Video RAM Cacheable
Select Enabled allows caching of the video RAM, resulting in better system per-
formance. However, if any program writes to this memory area, a system error
may occur.
VGA Share Memory Size
The share memory sizes for VGA are 8MB, 16MB and 32MB selectable, also you
can set it to “Disabled”, but be careful if you set this option “Disabled” without
an AGP card installed on the mainboard, you will find that no video at all when
you try to boot up. To correct the problem, you should clear the BIOS CMOS
(
! )*C +C $ C
CPU & PCI Bus Control
When you select this field the following menu will appear:
Managing The PC BIOS
! 3%3
! 3%3
! !3
! !3
! #)
; *
$
!!
- !#/'''(4
4=/#&
G H
G H
G H
G H
G H
