AXIOMTEK SBC84833 Series, User Manual

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SBC84833 Series All-In-One Capa Board User’s Manual
AMI BIOS SETUP UTILITY
64
z North Bridge Configuration
¾ DRAM Frequency
Use this item to control the Memory Clock.
¾ Configure DRAM Timing by SPD
Use this item to enable or disable DRAM timing by SPD (Serial
Presence Detect) device, which is a small EEPROM chip on the
memory module, containing important information about the module
speed, size, addressing mode and various parameters.
¾ Memory Hole
This area of system memory can be reserved for ISA adapter ROM.
When this area is reserved it cannot be cached. Check the user
information of peripherals that need to use this area of system
memory for the memory requirements. Here are the options,
Disabled
and 15M-16M .