GATING MODES
Triggering can be suppressed by a TTL-level signal on the rear-panel GATE connector.
The instrument can be set to stop triggering when this input high or low, using the front-
panel gate menu or the appropriate programming commands. When gated, the output
will complete the full pulse width if the output is high, and then stop triggering. Pulses
are not truncated.
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Summary of Contents for AVR-E1-B
Page 35: ...PCB 158R4 LOW VOLTAGE POWER SUPPLY...
Page 36: ...PCB 235B HIGH VOLTAGE DC POWER SUPPLY...
Page 37: ...PCB 151D RANGE POLARITY RELAY BOARD...
Page 46: ...PERFORMANCE CHECKSHEET 46...