Figure C
As before, if the delay is negative, the order of the SYNC and OUT pulses is reversed.
The last figure illustrates the relationship between the signal when an external TTL-level
trigger is used in the PW
IN
=PW
OUT
mode. In this case, the output pulse width equals the
external trigger’s pulse width (approximately), and the delay circuit is bypassed:
Figure D
The delay, pulse width, and frequency (when in the internal mode), of the OUT pulse
can be varied with front panel controls or via the GPIB or RS-232 computer interfaces.
SYNC OUT
100 ns, FIXED
MAIN OUTPUT
PULSE WIDTH
DELAY > 0
AMPLITUDE,
VARIABLE
3V, FIXED
> 50 ns
TTL LEVELS
(0V and 3V-5V)
TRIG
(external input)
PROPAGATION DELAY (FIXED)
MAIN OUTPUT
PW
OUT
≈ PW
IN
AMPLITUDE,
VARIABLE
TTL LEVELS
(0V and 3V-5V)
TRIG
(external input)
PROPAGATION DELAY (FIXED)
PW
IN
21
Summary of Contents for 14156
Page 29: ...value This completes the operational check 29...
Page 35: ...WIRING DIAGRAMS WIRING OF AC POWER...
Page 36: ...PCB 158R5 LOW VOLTAGE POWER SUPPLY...
Page 37: ...PCB 170C HIGH VOLTAGE POWER SUPPLY...
Page 39: ...PCB 94H ALARM BOARD...
Page 40: ...PCB 104G KEYPAD DISPLAY BOARD...
Page 41: ...MAIN WIRING POSITIVE UNITS P...
Page 42: ...PERFORMANCE CHECKSHEET 42...