RFSoC Development Kit Getting Started Guide
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Figure 11 - Launching RFSoC Explorer
Shown in
is the mapping of RFSoC data converters on ZCU111 that connect to signal paths
of the Qorvo RF card. ‘Tile’ and ‘Block’ indices are zero-based. For ADCs, Block (0 => 01; 1 = >23).
Qorvo Signal
CH2_RX
CH2_DPD
CH1_RX
CH1_DPD
CH2_TX
CH1_TX
AMC/Schem.
ADC_01
ADC_03
ADC_05
ADC_07
DAC_00
DAC_06
Tile
0
1
2
3
0
1
Block
1
1
1
1
0
2
Figure 12 - Channel map of ZCU111 data converters
From the main tab of RFSoC Explorer set the Board IP Address that was previously found using the
ifconfig
command from the host PC serial terminal connection to Linux running on the ZCU111.
Frequency Planning
Frequency planning involves selecting appropriate sampling rates, Nyquist zone of operation and digital signal
processing according to signal bandwidth, I/F frequency and board-level filtering. In this case the bandwidth
of LTE-band-3 is 75 MHz, centered at 1842 MHz in the downlink.
While the bandwidth of the RF-ADC could easily support direct-RF conversion of the 1842 MHz I/F in the first-
Nyquist zone, the relatively small instantaneous signal bandwidth of 75 MHz would make such an approach
wasteful of resources and power. We shall instead aim to match the response of the digital halfband filters in
the decimation stage of the digital downconverter (DDC) to the bandwidth of the LTE Band-3 signal.
