3-Feb-2015
4
Table 1
– DDR3L Connections
Signal Name
Description
Zynq AP SOC pin
DDR3 pin
DDR_CK_P
Differential clock output
L2
J7
DDR_CK_N
Differential clock output
M2
K7
DDR_CKE
Clock enable
N3
K9
DDR_CS_B
Chip select
N1
L2
DDR_RAS_B
RAS row address select
P4
J3
DDR_CAS_B
RAS column address select
P5
K3
DDR_WE_B
Write enable
M5
L3
DDR_BA[2:0]
Bank address
PS_DDR_BA[2:0]
BA[2:0]
DDR_A[14:0]
Address
PS_DDR_A[14:0]
A[14:0]
DDR_ODT
Output dynamic termination
N5
K1
DDR_RESET_B
Reset
B4
T2
DDR_DQ[31:0]
I/O Data
PS_DDR_DQ[31:0]
DDR3_DQ[15:0] x2
DDR_DM[3:0]
Data mask
PS_DDR_DM[3:0]
LDM/UDM x2
DDR_DQS_P[3:0]
I/O Differential data strobe
PS_DDR_DQS_P[3:0]
UDQS/LDQS x2
DDR_DQS_N[3:0]
I/O Differential data strobe
PS_DDR_DQS_N[3:0]
UDQS#/LDQS# x2
DDR_VRP
I/O Used to calibrate input
termination
H5
N/A
DDR_VRN
I/O Used to calibrate input
termination
G5
N/A
DDR_VREF[1:0]
I/O Reference voltage
P6 / H6
VTTREF
2.2.2
Quad-SPI Flash
PicoZed 7010/7020 features a 4-bit SPI (quad-SPI) serial NOR flash. The Spansion S25FL128S
(S25FL128SAGBHIA00) is used on this board. The Multi-I/O SPI Flash memory is used to
provide non-volatile boot, application code, and data storage. It can be used to initialize the PS
subsystem as well as configure the PL subsystem (bitstream). Spansion provides Spansion Flash
File System (FFS) for use after booting the Zynq-7000 AP SoC.
The relevant device attributes are:
128Mbit
o
Optional densities are available via customization
x1, x2, and x4 support
Speeds up to 104 MHz, supporting Zynq configuration rates @ 100 MHz
o
In Quad-SPI mode, this translates to 400Mbs
Powered from 3.3V
The Quad-SPI Flash connects to the Zynq PS QSPI interface. This requires connection to
specific pins in MIO Bank 0/500, specifically MIO[1:6,8] as outlined in the Zynq TRM. Quad-SPI
feedback mode is used, thus qspi_sclk_fb_out/MIO[8] is connected to a 20K pull-up resistor to
3.3V and nothing else. This allows a QSPI clock frequency greater than FQSPICLK2. The 20K
pull-up straps VMODE[1], setting the Bank 1 Voltage to 1.8V.
Table 2
– Quad-SPI Flash Pin Assignment and Definitions
Signal Name
Description
Zynq Pin
MIO
Quad-SPI Pin
CS
Chip Select
A7 (MIO Bank 0/500)
1
C2
DQ0
Data0
B8 (MIO Bank 0/500)
2
D3
DQ1
Data1
D6 (MIO Bank 0/500)
3
D2
DQ2
Data2
B7 (MIO Bank 0/500)
4
C4
DQ3
Data3
A6 (MIO Bank 0/500)
5
D4
SCK
Serial Data Clock
A5 (MIO Bank 0/500)
6
B2
FB Clock
QSPI Feedback
D5 (MIO Bank 0/500)
8
N/A
Note:
The QSPI data and clock pins are shared with the VMODE set resistors and the BOOT
MODE select jumper JT4 and switch SW1.
