FMC-HDMI-CAM + PYTHON-1300-C
Frame Buffer Design Tutorial
v2015_4
23 February 2016
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Reference Design Overview
The example design uses the Zynq processing system (PS) to initialize the PYTHON-1300-
C camera, the HDMI input interface, as well as the HDMI output interface. The design
also implements a simple image sensor pipeline (ISP) and video frame buffer inside the
programmable logic (PL).
The following figure illustrates the block diagram for the programmable logic (PL)
hardware implementation.
Figure 2 – FMC-HDMI-CAM + PYTHON-1300 Camera Reference Design –
Hardware Block Diagram
Valid licenses (hardware evaluation, or full license) are required for the following video
IP cores:
Color Filter Array Interpolation (CFA) v7.0
Chroma Resampler v4.0
Video On Screen Display (OSD) v6.0
RGB to YcrCb Color-Space Converter v7.1
Video Timing Controller (VTC) v6.1
HDMI
Output
AXI4S
To
Video
VTC
OSD
PYTHON
Receiver
Video
To
AXI4S
CFA
RGB
To
YUV
444
To
422
AXI
VDMA
Video
To
AXI4S
AXI
VDMA
HDMI
Input
