Avnet COM Express MSC C6C-AL User Manual Download Page 92

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MSC C6C-AL

MSC C6C-AL User Manual

92 / 128

6.9.9

PCI Express Configuration

Feature

Options

Description

PCI Express Clock Gating

Enabled, Disabled, Auto

Control the PCI Express Root Port. Auto: To disable unused root
por automatically for most optimum power savings.

Port8xh Decode Port

Enabled, Disabled

Select which PCI Express Root Port should claim accesses to I/O
port 8xh

Peer Memory Write Enable

Enabled, Disabled

Peer Memory write Enable/Disable

Compliance Mode

Enabled, Disabled

Compliance Mode Enable/Disable

PCIE Express Root Port 0-3

Submenu

Configure PCIE Express Root Port Settings

6.9.10 PCIE Express Root Port 0-3

Feature

Options

Description

PCI Express Root Port x

Enabled
Disabled

Control the PCI Express Root Port.

ASPM

Enabled
Disabled

PCI Express Active State Power Management settings.

L1 Substances

Disabled

L1.1

L1.2

L1.1 & L1.2

PCI Express L1 Substates settings.

ACS

Enabled
Disabled

Enable/Disable Access Control Services Extended Capability

URR

Enabled
Disabled

PCI Express Unsupported Request Reporting Enable/Disable.

Summary of Contents for COM Express MSC C6C-AL

Page 1: ...COM ExpressTM Compact Module MSC C6C AL Type 6 Pinout Intel AtomTM Celeron Pentium Series SOC Rev 1 0 2021 03 08 User Manual ...

Page 2: ...for any particular purpose is implied The information in this document is provided as is and is subject to change without notice EMC Rules This unit has to be installed in a shielded housing If not installed in a properly shielded enclosure and used in accordance with the instruction manual this product may cause radio interference in which case the user may be required to take adequate measures a...

Page 3: ...ntacting Avnet Integrated MSC Technical Support please consult the respective pages on our web site at www msc technologies eu for the latest documentation drivers and software downloads If the information provided there does not solve your problem please contact our Avnet Integrated MSC Technical Support Phone 49 8165 906 200 Email support msc technologies eu ...

Page 4: ... 11 Miscellaneous 36 2 12 12 Power and System Management 37 2 12 13 General Purpose I O 39 2 12 14 SDIO 39 2 12 15 SPI Interface 40 2 12 16 Module Type Definition 41 2 12 17 Power and GND 42 2 13 Pin List for MSC C6C AL Module Type 6 42 3 JUMPERS AND CONNECTORS 48 3 1 Jumpers 48 3 2 Fan Connector 49 3 3 Camera Connector 49 4 WATCHDOG 50 5 SYSTEM RESOURCES 51 5 1 PCI IRQ Routing 51 5 2 SMB Address ...

Page 5: ...Configuration 88 6 9 6 South Cluster Configuration 89 6 9 7 HD Audio Configuration 90 6 9 8 LPSS Configuration 91 6 9 9 PCI Express Configuration 92 6 9 10 PCIE Express Root Port 0 3 92 6 9 11 SATA Drives 95 6 9 12 SCC Configuration 95 6 9 13 USB Configuration 96 6 9 14 Miscellaneous Configuration 96 6 10 Security 98 6 10 1 Secure Boot 98 6 10 2 Key Management 99 6 11 Boot 102 6 12 Save Exit 104 6...

Page 6: ...MSC C6C AL MSC C6C AL User Manual 6 128 Revision History Rev Date Description 1 0 2021 03 08 First Release ...

Page 7: ...r3b pdf http www t13 org 4 Serial ATA Specification Serial ATA 1 0 gold pdf Last update August 29th 2002 Rev 1 0 http www sata io org 5 IEEE Std 802 3 2002 802 3 2002 pdf http www ieee org 6 VESA Embedded DisplayPort Standard eDP_v1_3 mem pdf Last update 13 01 2012 http www vesa org 7 Universal Bus Specification usb_20 pdf Last update April 27th 2000 http www usb org 8 Universal Serial Bus Revisio...

Page 8: ...result in minor or moderate injury All safety messages have a safety alert symbol and are structured as follows Danger Warning or Caution Type of hazard Potential consequences of the hazard Evasive or avoidance actions to be taken Notice Notices contain important information that should be observed In case of neglect the board can be damaged All notices have the symbol and are structured as follow...

Page 9: ...ly 1 6 Electrostatic Sensitive Device The MSC COM Express Compact Module is an electrostatic sensitive device It is packed accordingly NOTICE Handle the Compact Module at electrostatic free workstations only NOTICE Do not handle or store the Compact Module near strong electrostatic electromagnetic magnetic or radioactive fields unless the Compact Module is contained within its original packaging ...

Page 10: ...os Top Side View 1 Top Side Memory Socket 2 MAC Address Label 3 Layout Revision 4 Board Identification Number BID 5 Board ID Label 6 BIOS Label 7 Camera Interface Connector 8 System On Chip SOC 9 Micro SD Card Connector 10 Fan Connector 2 1 3 4 5 6 7 8 9 10 ...

Page 11: ...MSC C6C AL MSC C6C AL User Manual 11 128 Bottom Side View 11 Bottom side memory socket 12 COM Express connector 11 12 ...

Page 12: ...e together with power efficiency For evaluation and design in of the COM Express modules MSC offers evaluation baseboards and development motherboards providing the interface infrastructure for the COM Express module using PC type connectors for external access Currently four module sizes are defined in the COM Express Specification 2 1 the Mini Module the Compact Module the Basic Module and the E...

Page 13: ... PCIe Gen 2 switch Support pins for two Express Cards Display interfaces o three independent display controllers o Digital Display Interface DDI configurable as HDMI DVI or Display Port o Dual 24 bit LVDS channel shared with eDP High definition digital audio interface external CODEC Single GBit Ethernet interface Intel Ethernet Controller I210 AT LPC interface Two high speed UART ports TX and RX o...

Page 14: ...MSC C6C AL MSC C6C AL User Manual 14 128 2 3 Block Diagram ...

Page 15: ...el 2x24 Bit A B eDP on LVDS CH A pins 0 1 1 A B VGA Port 0 1 0 A B TV Out NA 0 A B DDI 0 NA 0 A B Serial Ports 1 2 0 2 2 HSUART Functionality based on the 16550 and 16750 industry standards HSUART Slave Mode is not supported Serial Infrared SIR per the Infrared Data Association IrDA 1 0 is not supported A B CAN interface on SER1 0 1 0 A B SATA Ports 1 4 2 SATA 6 0 GBit s A B HDA Digital Interface ...

Page 16: ... SMBus 1 1 1 A B I2 C 1 1 1 A B Watchdog Timer 0 1 1 A B Speaker Out 1 1 1 A B External BIOS ROM support 0 2 1 A B Reset Functions 1 1 1 Power Management A B Thermal Protection 0 1 0 A B Battery Low Alarm 0 1 1 A B Suspend 0 1 1 A B Wake 0 2 2 A B Power Button Support 1 1 1 A B Power Good 1 1 1 A B VCC_5V_SBY Contacts 4 4 4 A B Sleep Input 0 1 1 A B Lid Input 0 1 1 A B Fan Control Signals 0 2 2 A ...

Page 17: ...buffered DDR3L Maximal height 1250mil 31 75mm PC3L 10600 PC3L 12800 PC3L 14900 DDR3L SDRAM DDR3L 1333 DDR3L 1600 DDR3L 1866 Intel CeleronTM SKU PC3L 10600 PC3L 12800 DDR3L SDRAM DDR3L 1333 DDR3L 1600 Module topside socket should be filled first SATA 2 SATA channels up to 6 0 GBit s USB 8 x USB 2 0 4 x USB 3 0 COM Express Type 6 interface fully compliant to COM Express Base Specification R2 1 PCI E...

Page 18: ... and system reset TPM TPM module TPM 2 0 SLB9670 Fan Supply 4 pin header for support of a 12V PWM fan Real Time Clock RTC integrated in Intel SOC CMOS Battery External System Monitoring Voltages temperatures fan Core voltage 3 3V onboard voltage 12V input voltage 5V SBY input voltage CPU temperature 40 C 110 C SKU dependent System memory temperature Board temperature Fan speed and automatic fan sp...

Page 19: ...tion 2 7 1 Running Mode All measurements were made by plugging the MSC C6C AL module onto a MSC MB EVA6 carrier The module was equipped with two 4GByte memory modules M3ST 4GMSCDPC P 4GB DDR3L 1600 W T SODIMM The table below shows typical values which refer to consumption of the module itself without consumption of the base board and CPU fan The following applications have been tested with minimum...

Page 20: ...3L 3 0 W 14 9 W 15 3 W 7 6 W C6C AL E3950 N5261I Intel AtomTM x7 E3950 4C 1 60GHz 2 00GHz 2MiB L2 Cache 12W 2ch DDR3L 3 1 W 20 6 W 24 4 W 8 7 W C6C AL N3350 N4261C Intel CeleronTM N3350 2C 1 10GHz 2 40GHz 2MiB L2 Cache 6W 2ch DDR3L 3 0 W 9 0 W1 20 5 W1 7 2 W C6C AL N4200 N5261C Intel PentiumTM N4200 4C 1 10GHz 2 50GHz 2MiB L2 Cache 6W 2ch DDR3L 3 2 W 11 0 W1 26 3 W1 10 9 W 1 TAT workload setting C...

Page 21: ... Intel AtomTM x5 E3930 2C 1 30GHz 1 80GHz 2MiB L2 Cache 6 5W 2ch DDR3L 5V_SBY 0 64 W 0 47 W C6C AL E3940 N5261I Intel AtomTM x5 E3940 4C 1 60GHz 1 80GHz 2MiB L2 Cache 9 5W 2ch DDR3L 5V_SBY 0 44 W 0 27 W C6C AL E3950 N5261I Intel AtomTM x7 E3950 4C 1 60GHz 2 00GHz 2MiB L2 Cache 12W 2ch DDR3L 5V_SBY 0 46 W 0 30 W C6C AL N3350 N4261C Intel CeleronTM N3350 2C 1 10GHz 2 40GHz 2MiB L2 Cache 6W 2ch DDR3L...

Page 22: ...he following demands 204pin unbuffered non ECC DDR3L SO DIMM 1 35V Supply Voltage DDR3L 1333 PC3L 10600 DDR3L 1600 PC3L 12800 DDR3L 1867 PC3L 14900 Maximum module height 1250mil 31 75mm SPD Serial Presence Detect EEPROM Maximum system capacity is 8GB NOTICE When using only one memory module insert it into the socket on the topside of the module ...

Page 23: ... specification 5mm and 8mm The height option is defined by the connectors on the baseboard The modules with AtomTM APL I CPUs are equipped with an integrated heat spreader This heat spreader adds 1 00 mm to CPU height against modules with CPUs without integrated heat spreader This has no effect to the z height of a module with mounted spreader ...

Page 24: ...e possible to interchange different module types without problems There must be a cooling solution for the system The surface temperature of the heat spreader should not exceed 80 C Main issue for the thermal functionality of a system is that each device of the module is operated within its specified thermal values The max value for the SOC is 110 C T die So there may be system implementations whe...

Page 25: ...nd for input and I O pins with the input voltage tolerance The pin power rail and the pin input voltage tolerance may be different For example the PCI group is defined as having a 3 3V power rail meaning that the output signals will only be driven to 3 3V but the pins are tolerant of 5V signals An additional label Sus indicates that the pin is active during suspend states S3 S4 S5 If suspend modes...

Page 26: ...pe Signal Level Power Rail Remark Tolerance PU PD SR Description Source Target GBE0_MDI 0 3 GBE0_MDI 0 3 I O Analog 3 3V Sus 3 3V Gigabit Ethernet Controller 0 Media Dependent Interface Differential Pairs 0 1 2 3 The MDI can operate in 1000 100 and 10 Mbit sec modes MDI 0 B1_DA MDI 1 B1_DB MDI 2 B1_DC MDI 3 B1_DD Intel I210 AT GBE0_ACT OD CMOS 3 3V Sus 5V 20 mA Gigabit Ethernet Controller 0 activi...

Page 27: ...Description Source Target PCIE_TX 0 1 PCIE_TX 0 1 O PCIe 1 0V AC coupled on module PCI Express Differential Transmit Pairs 0 through 2 AL SOC PCIE_RX 0 1 PCIE_RX 0 1 I PCIe 1 0V AC coupled off module PCI Express Differential Receive Pairs 0 through 2 AL SOC PCIE_TX 2 4 PCIE_TX 2 4 O PCIe 1 0V AC coupled on module PCI Express Differential Transmit Pairs 3 through 4 Gen2 switch PCIE_RX 2 4 PCIE_RX 2...

Page 28: ...3V USB differential pairs channels 5 through 7 AL SOC USB_0_1_OC I CMOS 3 3V Sus 3 3V ePU 4 7 KΩ USB channels 0 and 1 over current sense A pull up for this line is present on the module An open drain driver from a USB current monitor on the Carrier Board may drive this line low Do not pull this line high on the Carrier Board AL SOC USB_2_3_OC I CMOS 3 3V Sus 3 3V ePU 4 7 KΩ USB channels 2 and 3 ov...

Page 29: ...ne high on the Carrier Board AL SOC USB_SSTX 0 3 USB_SSTX 0 3 O USB 3 0 1 0V sus AC coupled on module USB 3 0 Differential Transmit Pairs 0 through 3 AL SOC USB_SSRX 0 3 USB_SSRX 0 3 I USB 3 0 1 0V sus AC coupled off module USB 3 0 Differential Receive Pairs 0 through 3 AL SOC NOTICE Considerable care must be taken when using high speed signals on the carrier board Reliable functionality depends o...

Page 30: ...C multiplexed address command and data bus AL SOC LPC_FRAME O CMOS 3 3V LPC frame indicates the start of an LPC cycle AL SOC LPC_DRQ0 I CMOS 3 3V 3 3V LPC serial DMA request not available LPC_DRQ1 I CMOS 3 3V LPC serial DMA request not available LPC_SERIRQ I OD CMOS 3 3V 3 3V ePU 10 KΩ LPC serial interrupt AL SOC LPC_CLK O CMOS 3 3V eSR 10 Ω LPC clock output 33MHz nominal AL SOC ...

Page 31: ...A71 eDP_TX2 LVDS_A0 A72 eDP_TX2 LVDS_A1 A73 eDP_TX1 LVDS_A1 A74 eDP_TX1 LVDS_A2 A75 eDP_TX0 LVDS_A2 A76 eDP_TX0 LVDS_A_CK A81 eDP_TX3 LVDS_A_CK A82 eDP_TX3 LVDS_VDD_EN A77 eDP_VDD_EN LVDS_BKLT_EN B79 eDP_BKLT_EN LVDS_BKLT_CTRL B83 eDP_BKLT_CTRL LVDS_I2C_CK A83 eDP_AUX LVDS_I2C_DAT A84 eDP_AUX RSVD A87 eDP_HPD ...

Page 32: ...OS 3 3V LVDS panel backlight enable Embedded Controller LVDS_BKLT_CTRL O CMOS 3 3V eSR 49 9 Ω LVDS panel backlight brightness control Embedded Controller LVDS_I2C_CK O CMOS 3 3V ePU 2 2 KΩ I2C clock output for LVDS display use ANX1122 LVDS_I2C_DAT I OD CMOS 3 3V 3 3V ePU 2 2 KΩ I2C data line for LVDS display use ANX1122 2 12 8 2 eDP Signal Pin Type Signal Level Power Rail Remark Tolerance PU PD SR...

Page 33: ...ay Interfaces 2 12 9 1 Overview Type6 DDI Video Type Mapping Signal DP HDMI DVI TMDS Signaling DDI1 DDI1_PAIR0 DP1_LANE0 TMDS1_DATA2 DDI1_PAIR1 DP1_LANE1 TMDS1_DATA1 DDI1_PAIR2 DP1_LANE2 TMDS1_DATA0 DDI1_PAIR3 DP1_LANE3 TMDS1_DATACLK DDI1_HPD DP1_HPD HDMI1_HPD DDI1_CTRLCLK DATA_AUX DP1_AUX HDMI1_CTRLCLK DATA DDI1_DDC_AUX_SEL DDI2 DDI2_PAIR0 DP2_LANE0 TMDS2_DATA2 DDI2_PAIR1 DP2_LANE1 TMDS2_DATA1 DD...

Page 34: ...module DisplayPort Lane 0 3 differential pairs AL SOC DP2_AUX DP2_AUX I O AC coupled on module ePD 100KΩ ePU 100KΩ DisplayPort Aux control channel differential pair AL SOC DP2_HPD I CMOS 3 3V 3 3V ePD 100KΩ DisplayPort Hot Plug Detect AL SOC DDI2_DDC_AUX_SEL I CMOS 3 3V 3 3V ePD 1MΩ If this input is floating the AUX pair is used for the DP AUX signals If pulled high the AUX pair contains the CTRLC...

Page 35: ... ePD 1MΩ Pull to 3 3V on the Carrier with 100k Ohm resistor to configure the DDI1_AUX pair as the DDC channel TMDS2_DATA 0 3 TMDS2_DATA 0 3 O TMDS AC coupled off module HDMI DVI TMDS Data 0 3 output differential pairs AL SOC TMDS2_DATACLK TMDS2_DATACLK O TMDS AC coupled off module HDMI DVI TMDS Clock differential pairs AL SOC HDMI2_CTRLCLK I O CMOS 3 3V 3 3V ePD 100KΩ HDMI DVI Control Clock Shared...

Page 36: ...Source Target I2C_CK I O CMOS 3 3V Sus 3 3V ePU 2 2 KΩ General purpose I2C port clock output AL SOC I2C_DAT I O CMOS 3 3V Sus 3 3V ePU 2 2 KΩ General purpose I2C port data I O line AL SOC SPKR O CMOS 3 3V 3 3V 7mA Output for audio enunciator the speaker in PC AT systems AL SOC BIOS_DIS 1 I CMOS 3 3V ePU 10 KΩ Module BIOS disable input BIOS_DIS 0 I CMOS 3 3V ePU 10 KΩ Module BIOS disable input not ...

Page 37: ...LPC devices AL SOC SUS_S3 O CMOS 3 3V Sus 3 3V 7mA Indicates system is in Suspend to RAM state Active low output AL SOC SUS_S4 O CMOS 3 3V Sus 3 3V 7mA Indicates system is in Suspend to Disk state Active low output Shorted to SUS_S5 AL SOC SUS_S5 O CMOS 3 3V Sus 3 3V 7mA Indicates system is in Soft Off state Also known as PS_ON and can be used to control an ATX power supply AL SOC WAKE0 I CMOS 3 3...

Page 38: ... Embedded Controller SMB_CK I O OD CMOS 3 3V Sus 3 3V ePU 2 2 KΩ System Management Bus bidirectional clock line Power sourced through 3 3V standby rail AL SOC Embedded Controller SMB_DAT I O OD CMOS 3 3V Sus 3 3V ePU 2 2 KΩ System Management Bus bidirectional data line Power sourced through 3 3V standby rail AL SOC Embedded Controller SMB_ALERT I CMOS 3 3V Sus 3 3V ePU 2 2 KΩ System Management Bus...

Page 39: ...d support AL SOC SDIO_CLK GPO0 O CMOS 1 8V 3 3V 1 8V 3 3V iPD 20 KΩ SDIO Clock With each cycle of this signal a one bit transfer on the command and each data line occurs This signal has maximum frequency of 48 MHz This pin is mapped to GPO0 AL SOC SDIO_CMD GPO1 O CMOS 1 8V 3 3V 1 8V 3 3V iPU 20 KΩ SDIO Command Response This signal is used for card initialization and for command transfers During in...

Page 40: ...from Module to Carrier SPI AL SOC SPI_POWER O Power 1 8V Sus Power supply for Carrier Board SPI sourced from Module nominally 3 3V The Module shall provide a minimum of 100mA on SPI_POWER Carriers shall use less than 100mA of SPI_POWER SPI_POWER shall only be used to power SPI devices on the Carrier BIOS_DIS 1 0 I CMOS 3 3V Sus 3 3V ePU 10 KΩ Selection straps to determine the BIOS boot device BIOS...

Page 41: ...TYPE pins and keeps power off e g deactivates the ATX_ON signal for an ATX power supply if an incompatible module pin out type is detected The Carrier Board logic may also implement a fault indicator such as a LED Carrier board logic TYPE10 O No connect on COM 0 Rev 2 1 Module Type 6 Dual use pin Indicates to the Carrier Board that a Type 10 Module is installed Indicates to the Carrier that a Rev ...

Page 42: ...V SUS regulator VCC_RTC Power Real time clock circuit power input 3 0V 2 5V to 3 47V AL SOC GND Power Ground DC power and signal and AC signal return path All available GND connector pins shall be used and tied to Carrier Board GND plane 2 13 Pin List for MSC C6C AL Module Type 6 Row A Row B Row C Row D A1 GND FIXED B1 GND FIXED C1 GND FIXED D1 GND FIXED A2 GBE0_MDI3 B2 GBE0_ACT C2 GND D2 GND A3 G...

Page 43: ... D16 DDI1_CTRLDATA_AUX A17 SATA0_TX B17 SATA1_TX C17 RSVD D17 RSVD A18 SUS_S4 B18 SUS_STAT C18 RSVD D18 RSVD A19 SATA0_RX B19 SATA1_RX C19 PCIE_RX6 D19 PCIE_TX6 A20 SATA0_RX B20 SATA1_RX C20 PCIE_RX6 D20 PCIE_TX6 A21 GND FIXED B21 GND FIXED C21 GND FIXED D21 GND FIXED A22 SATA2_TX B22 SATA3_TX C22 PCIE_RX7 D22 PCIE_TX7 A23 SATA2_TX B23 SATA3_TX C23 PCIE_RX7 D23 PCIE_TX7 A24 SUS_S5 B24 PWR_OK C24 D...

Page 44: ..._CTRLDATA_AUX D37 DDI1_PAIR3 A38 USB_6_7_OC B38 USB_4_5_OC C38 DDI3_DDC_AUX_SEL D38 RSVD A39 USB4 B39 USB5 C39 DDI3_PAIR0 D39 DDI2_PAIR0 A40 USB4 B40 USB5 C40 DDI3_PAIR0 D40 DDI2_PAIR0 A41 GND FIXED B41 GND FIXED C41 GND FIXED D41 GND FIXED A42 USB2 B42 USB3 C42 DDI3_PAIR1 D42 DDI2_PAIR1 A43 USB2 B43 USB3 C43 DDI3_PAIR1 D43 DDI2_PAIR1 A44 USB_2_3_OC B44 USB_0_1_OC C44 DDI3_HPD D44 DDI2_HPD A45 USB...

Page 45: ...G_RX2 D58 PEG_TX2 A59 PCIE_TX3 B59 PCIE_RX3 C59 PEG_RX2 D59 PEG_TX2 A60 GND FIXED B60 GND FIXED C60 GND FIXED D60 GND FIXED A61 PCIE_TX2 B61 PCIE_RX2 C61 PEG_RX3 D61 PEG_TX3 A62 PCIE_TX2 B62 PCIE_RX2 C62 PEG_RX3 D62 PEG_TX3 A63 GPI1 B63 GPO3 C63 RSVD D63 RSVD A64 PCIE_TX1 B64 PCIE_RX1 C64 RSVD D64 RSVD A65 PCIE_TX1 B65 PCIE_RX1 C65 PEG_RX4 D65 PEG_TX4 A66 GND B66 WAKE0 C66 PEG_RX4 D66 PEG_TX4 A67 ...

Page 46: ...GND FIXED C80 GND FIXED D80 GND FIXED A81 LVDS_A_CK B81 LVDS_B_CK C81 PEG_RX9 D81 PEG_TX9 A82 LVDS_A_CK B82 LVDS_B_CK C82 PEG_RX9 D82 PEG_TX9 A83 LVDS_I2C_CK B83 LVDS_BKLT_CTRL C83 RSVD D83 RSVD A84 LVDS_I2C_DAT B84 VCC_5V_SBY C84 GND D84 GND A85 GPI3 B85 VCC_5V_SBY C85 PEG_RX10 D85 PEG_TX10 A86 RSVD B86 VCC_5V_SBY C86 PEG_RX10 D86 PEG_TX10 A87 eDP_HPD B87 VCC_5V_SBY C87 GND D87 GND A88 PCIE0_CK_R...

Page 47: ...B100 GND FIXED C100 GND FIXED D100 GND FIXED A101 SER1_TX B101 FAN_PWNOUT C101 PEG_RX15 D101 PEG_TX15 A102 SER1_RX B102 FAN_TACHIN C102 PEG_RX15 D102 PEG_TX15 A103 LID B103 SLEEP C103 GND D103 GND A104 VCC_12V B104 VCC_12V C104 VCC_12V D104 VCC_12V A105 VCC_12V B105 VCC_12V C105 VCC_12V D105 VCC_12V A106 VCC_12V B106 VCC_12V C106 VCC_12V D106 VCC_12V A107 VCC_12V B107 VCC_12V C107 VCC_12V D107 VCC...

Page 48: ...ule BIOS Default By shorting the pins of this jumper during boot the values of the BIOS setup will be reset to default values BIOS Recovery By shorting the pins of this jumper during boot the system is forced into crisis recovery mode For more information see chapter 6 18 These jumpers are located at the top side of the board on the edge of the PCB see photo BIOS Recovery Layout Revision ...

Page 49: ...nput range at more than 12V can damage the fan The correct function of the fan is not guaranteed below 12V 3 3 Camera Connector The camera connector with a MIPI interface for CSI 2 0 camera support is located at top side of the CPU module directly beneath the memory socket The following connector type is used Hirose FH12A 36S 0 5SH A camera module can be connected with a suitable 36 pin flex foil ...

Page 50: ... CAM1_CSI_CLK MIPI CSI 2 0 D PHY 1 2 Clock Lane 27 CAM1_CSI_CLK MIPI CSI 2 0 D PHY 1 2 Clock Lane 28 GND GND 29 CAM1_CSI_D0 MIPI CSI 2 0 D PHY 1 2 Data Lane 1 30 CAM1_CSI_D0 MIPI CSI 2 0 D PHY 1 2 Data Lane 1 31 CAM1_RST Camera 1 reset signal low active 1 8V 32 CAM1_CSI_D1 MIPI CSI 2 0 D PHY 1 2 Data Lane 0 33 CAM1_CSI_D1 MIPI CSI 2 0 D PHY 1 2 Data Lane 0 34 GND GND 35 CAM0_GPIO Camera 0 GPIO 1 8...

Page 51: ...2 PIRQ 3 PIRQ 4 PIRQ 5 PIRQ 6 PIRQ 7 or Onboard Device INT A INT B INT C INT D INT E INT F INT G INT H IGD 0x02 0 0 x IUNIT 0x03 0 0 x PMC 0x0D 1 0 x HDA 0x0E 0 0 x CSE 0x0F 0 0 x ISH 0x11 0 0 x SATA 0x12 0 0 x xHCI 0x15 0 0 x I2C4 0x17 0 0 x I2C5 0x17 1 0 x I2C6 0x17 2 0 x UART0 0x18 0 0 x UART1 0x18 1 0 x SDCard 0x1B 0 0 x EMMC 0x1C 0 0 x SMBus Controller 0x1f 1 0 x PCIE Root Port 0 0x13 0 0 a b...

Page 52: ...ress Map Device Address ANX1122 50h 28h ANX1122 8Ch 46h SO DIMM 0 SPD EEPROM A0h 50h SO DIMM 1 SPD EEPROM A2h 51h CMOS Backup EEPROM A8h 54h AAh 55h Embedded Controller C0h 60h Pericom PCIe switch DEh 6Fh 8 bit address with R W 7 bit address without R W ...

Page 53: ...ground While the startup screen is displayed press the Setup Entry key ESC or DEL The system acknowledges the input and at the end of POST the screen clears and setup launches Note By pressing F10 during POST system will display a Boot Menu for directly booting a selected device 6 4 Aptio Setup Utility With the AMI Aptio Setup program you can modify Aptio settings and control the special features ...

Page 54: ... North Bridge User Password System Information SMART Settings South Bridge HDD Security Configuration Firmware Update Serial Port Console Redirection Uncore Configuration Secure Boot CPU Configuration South Cluster Configuration AMI Graphic Output Protocol Policy PCI Subsystem Configuration Network Stack Configuration CSM Configuration NVMe Configuration SDIO Configuration USB Configuration Securi...

Page 55: ...ation Advanced Use this menu to set the Advanced Features available on your system s chipset Chipset Use this menu to set Chipset Features Security Use this menu to set User and Supervisor Passwords and the Backup and Virus Check reminders Boot Use this menu to set the boot order in which the BIOS attempts to boot to OS Save Exit Saves and Exits the Aptio setup utility Use the left and right arrow...

Page 56: ...Previous Values F3 Optimized Defaults F4 Save and Exit Esc Exit submenu Exit Setup utility without saving Select an item To select an item use the arrow keys to move the cursor to the field you want Then use the plus and minus value keys to select a value for that field Alternatively the Enter key can be used to select a value from a Pop Up menu The Save Values commands in the Exit Menu save the v...

Page 57: ...ows the Project Version Build Date and Time Informative Shows the Build Date Access Level Informative This feature shows what kind of user has entered the Aptio setup It depends on the Security Tab if an Administrator and or User password is set Board Info Submenu Shows board specific information Hardware Monitoring Submenu Shows the hardware sensors monitoring System Information Submenu Shows Sys...

Page 58: ...e highest temperature of the CPU ever measured Board Min Temperature Informative Shows the lowest temperature of the board ever measured Board Max Temperature Informative Shows the highest temperature of the board ever measured Memory Min Temperature Informative Shows the lowest temperature of memory ever measured Memory Max Temperature Informative Shows the highest temperature of memory ever meas...

Page 59: ...e Informative Shows CPU temperature Board Temperature Informative Shows the board temperature VCore Informative Shows the VCore voltage 3 3V Informative Shows the 3 3V voltage 5V Informative Shows the 5V voltage 5V Standby Informative Shows the current 5V Standby voltage 12V Informative Shows the 12V voltage Vbat Informative Shows the voltage of the RTC CPU Fan Speed Informative Shows the current ...

Page 60: ...g TXE Version GOP Driver Version 6 7 4 Firmware Update Feature Options Description Configure Update Bios Only Entire Flash BIOS only Update BIOS Region Entire Flash Update Entire Flash Preserve SMBIOS Variable Enabled Disabled If Enabled restore SMBIOS Variables DMI Table Preserve Boot Option Priorities Enabled Disabled If enabled restore Boot Option Priorities after Firmware Update This option do...

Page 61: ...bled preserve Network Settings Start Firmware Update Press Enter to Start a Firmware Update The BIOS Image has to be placed into the correct directory See above Caution Make sure if POST Watchdog is enabled a higher timeout as 60s is selected or disable POST Watchdog for the Bios Update otherwise Bios Update can become corrupt and system won t boot again On first boot or after Bios Update the syst...

Page 62: ...tional DNS Server Entry 0 in dotted decimal notation Note only visible if local address mode is set to static Optional DNS Server 2 DNS Server 2 Enter optional DNS Server Entry 0 in dotted decimal notation Note only visible if local address mode is set to static Optional DNS Server 3 DNS Server 3 Enter optional DNS Server Entry 0 in dotted decimal notation Note only visible if local address mode i...

Page 63: ...art Settings Serial Port Console Redirection Submenu Serial Port Console Redirection CPU Configuration Submenu CPU Configuration Parameters AMI Graphic Output Protocol Policy Submenu User Select Monitor Output by Graphic Output PCI Subsystem Settings Submenu PCI Subsystem Settings Network Stack Configuration Submenu Configuration for UEFI Network boot CSM Configuration Submenu CSM configuration En...

Page 64: ...CR Bank Enable Disable Enable or disable SHA 1 PCR Bank SHA256 PCR Bank Enable Disable Enable or disable SHA256 PCR Bank Pending operation None TPM Clear Schedule an Operation for the Security Device NOTE Your Computer will reboot during restart in order to change State of Security Device Platform Hierarchy Enable Disable Enable or Disable Platform Hierarchy Storage Hierarchy Enable Disable Storag...

Page 65: ...fective with some OS Lock Legacy Resources Enabled Disabled Set to enabled to prevent the OS from reconfiguring the resources of the SIO device through ACPI 6 8 3 SMART Settings Feature Options Description SMART Self Test Enabled Disabled Run SMART Self Test on all HDDs during POST 6 8 4 Serial Port Console Redirection Feature Options Description Com 0 and 1 Console Redirection Enabled Disabled Co...

Page 66: ...a Both computers should have the same or compatible settings 6 8 5 Console Redirection Submenu Feature Options Description Terminal Type ANSI VT100 VT100 VT UTF8 Emulation ANSI Extended ASCII char set VT100 ASCII char set VT100 Extends VT100 to support color function keys etc VT UTF8 Uses UTF8 encoding to map Unicode chars onto 1 or more bytes Bits per second 9600 19200 38400 57600 115200 Selects ...

Page 67: ... stop the data flow Once the buffers are empty a start signal can be sent to re start the flow Hardware flow control uses two wires to send start stop signals VTUF8 Combo Key Support Enabled Disabled Enable VT UF8 Combination Key Support for ANSI VT100 terminals Recorder Mode Disabled Enabled With this mode enabled only text will be sent This is to capture Terminal data Resolution 100x31 Disabled ...

Page 68: ...or Cores Enabled Disabled Number of cores to enable in each processor package Core 0 Enabled Disabled Core 0 Enable Core 1 Enabled Disabled Core 1 Enable Disable Core 2 Enabled Disabled Core 2 Enable Disable Core 3 Enabled Disabled Core 3 Enable Disable Intel Virtualization Technology Enabled Disabled When enabled a VMM can utilize the additional hardware capabilities provided by Vanderpool Techno...

Page 69: ...minimum speed when all cores enter C State Max Package C State C0 PC1 PC2 Controls the Max Package C State that the processor will support Max Core C State C1 C6 C7 C8 C9 C10 unlimited Fused Value This option controls the Max Core C State that cores will support C State Auto Demotion C1 Disabled Configure C State Auto Demotion C State Un demotion C1 Disabled Configure C State Un demotion Power Lim...

Page 70: ...ture Options Description Above 4G Decoding Enabled Disabled Globally Enables or Disables 64 bit capable Devices to be Decoded in Above 4G Adress Space Only if System Supports 64 bit PCI Decoding SR IOV Support Enabled Disabled If system has SR IOV capable PCIe Devices this option Enables or Disables Single Root IO Virtualization Support BME DMA Mitigation Enabled Disabled Re enable Bus Master Attr...

Page 71: ...Boot Support If disabled IPV6 HTTP boot option will not be created PXE boot wait time 1 5s Wait time to press ESC key to abort the PXE boot Media detect count 1 50 Number of times presence of media will be checked 6 8 11 CSM Configuration Feature Options Description CSM Support Enabled Disabled Enable Disable CSM Support This module is able to emulate legacy BIOS environment and allow booting lega...

Page 72: ...e network controller appears as boot device and can be used to boot via PXE Storage Do not launch UEFI only Legacy only Controls the execution of UEFI and Legacy Storage OPROM Video Do not launch UEFI only Legacy only Legacy first UEFI first Controls the execution of UEFI and Legacy Video OPROM NOTICE Legacy Video Bios is not supported by Intel for Apollo Lake It should only be used for specific d...

Page 73: ... ADMA SDMA PIO Auto Option Access SD device in DMA mode if controller supports it otherwise in PIO mode DMA Option Access SD device in DMA mode PIO Option Access SD device in PIO mode MMC Auto Floppy Forced FFD Hard Disk Mass storage device emulation type AUTO enumerates devices less than 530 MB as floppies Forced FDD Option can be used to force HDD formatted drive to boot as FDD ...

Page 74: ...t value for Control Bulk and Interrupt transfers Device reset time out 10 sec 20 sec 30 sec 40 sec USB mass storage device Start Unit command time out Device power up delay Auto Manual Maximum time the device will take before it properly reports itself to the Host Controller Auto uses default value for a Root port it is 100 ms for a Hub port the delay is taken from Hub descriptor Device power up d...

Page 75: ...nfiguration Feature Options Description WB627 COM A B Enabled Disabled Enable or disable COM A B on Winbond SIO WB627 COM A B Setting Auto I O 3F8h IRQ 4 I O 3F8h IRQ 3 4 5 6 7 10 11 12 I O 2F8h IRQ 3 4 5 6 7 10 11 12 I O 3E8h IRQ 3 4 5 6 7 10 11 12 I O 2E8h IRQ 3 4 5 6 7 10 11 12 Resource setting for COM A B on Winbond SIO WB627 LPT Disabled Enabled Enable or disable LPT on Winbond SIO Change Set...

Page 76: ...ing for LPT on Winbond SIO WB627 PS 2 Controller Disabled Enabled Enable or disable the WB627 PS 2 controller WB627 HWM Interface Disabled Enabled Enable or disable the hardware monitoring interface If enabled the base address 0x0290 will be used NOTE The above super IO menus will only appear if the SuperIO device is discovered on the carrier board ...

Page 77: ...ne how the fan should be controlled manually set to a fixed duty cycle or temperature based auto control Fan Speed Off 25 50 75 100 Setup the fan duty cycle for manual fan control By CPU sensor Enabled Disabled If enabled the cpu fan will be controlled by this temperature sensor By Board sensor Enabled Disabled If enabled the cpu fan will be controlled by this temperature sensor By Memory sensor E...

Page 78: ...h the fan should be set to maximum speed duty cycle NOTE This option depends on selected temperature source CPU System Board or a combination of these CPU Memory Board Temperature Limit T3 C 50 55 60 65 70 75 80 85 90 95 100 C Temperature threshold in degrees Celsius at which the fan should be set to maximum speed duty cycle NOTE This option depends on selected temperature source CPU System Board ...

Page 79: ...matic temperature control The System fan is typically associated with one of the external temperature sensors and is set to manual mode per default In temperature based mode up to three different sources can be selected CPU temperature board temperature sensor and system temperature sensor Temperature based mode controls fan within 4 temperature zones and fixed PWM duty cycles PWMmin 25 PWMmid 50 ...

Page 80: ...h maximum speed T1 Minimum temperature limit starting Fan selectable by SETUP T2 Temperature limit for medium Fan speed selectable by SETUP T3 Temperature limit for maximum Fan speed selectable by SETUP Thyst Temperature hysteresis selectable by SETUP Temperature Control with multiple Sensors Fan control allows the association of any temperature sensor supported by embedded controller This allows ...

Page 81: ...t temperature profiles for any temperature sensor can be selected in BIOS SETUP If more than one temperature sensor is selected for fan control the higher temperature exceeding the selected temperature limit T1 T2 T3 gets precedence for fan regulation ...

Page 82: ...t 1s 10s 30s 1min 5min Select the timeout value after which the watchdog will perform its reset action This timeout will start to countdown after the event timeout expires Reset Action Nothing Reset WDOUT WDOUT Reset Select the action that should take place after a reset timeout occurs POST Watchdog Enabled Disabled Enable a watchdog during bios POST before OS boot ATTENTION if this watchdog is co...

Page 83: ...e protect Enabled Disabled If enabled the SD Card will always be read only regardless of the state of the write protection pin User I2C Support GPIO based Controller based PCI mode Select the type of user I2C support GPIO based is for Windows and EAPI V4 or lower Select Controller based for Linux and Windows with EAPI V5 or higher Set User I2C Speed Standard Mode Fast Mode Select User I2C Speed LP...

Page 84: ... Low Output High Input GPIO Configuration NOTE On C6C AL the GPIO 0 3 can be configured Input and Output GPO 3 7 can only be Output 6 8 21 System Component Feature Options Description CRID Setting CRID_0 CRID_2 Disabled Select the Revision ID reflected in PCI config space OS Reset Select Warm Reset Cold Reset Select the reset type in FACP table DDR SSC Enabled Disabled Enable DDR Spread Spectrum C...

Page 85: ...ion table for HighSpeed SerialIO spread spectrum 6 9 Chipset Feature Options Description Flat Panel Configuration Submenu Flat Panel Configuration North Bridge Submenu North Bridge Settings South Bridge Submenu South Bridge Settings Uncore Configuration Submenu Uncore Configuration Settings South Cluster Configuration Submenu South Cluster Configuration ...

Page 86: ...of LVDS channels Single Channel 1bpp Dual Channel 2bpp Select number of pixels transferred per clock LVDS Spread Spectrum Disabled 0 25 1 75 Configure the spread spectrum for the LVDS interface LVDS Voltage Swing 100mV 400mV Configure the voltage swing for the LVDS interface Backlight Control Submenu Set Backlight settings 6 9 2 Backlight Control Feature Options Description Backlight_EN Control Ch...

Page 87: ...ess value of the flat panel PWM Frequency 200HZ 1KHz 10KHz 18KHz Select backlight PWM frequency for brightness control 6 9 3 North Bridge Feature Options Description Max TOLUD Dynamic 2GB 2 25 GB 2 5GB 2 75GB 3GB Maximum Value of TOLUD Above 4GB MMIO BIOS assignment Enabled Disabled Enable Disable above 4GB MemoryMappedIO BIOS assignment This is disabled automatically when Aperture Size is set to ...

Page 88: ... and IDI Agent Real Time Traffic Mask Bits 6 9 5 Uncore Configuration Feature Options Description GOP Driver Enabled Disabled Enable GOP Driver will unload VBIOS Disable it will load VBIOS Intel Graphics Pei Display Peim Enabled Disabled Enable Disable Pei Early Display GOP Brightness Level 0 255 Set GOP Brightness Level Value ranges from 0 255 VBT Select eDP 18 Bit Color LFP eDP 24 Bit Color LFP ...

Page 89: ...288MHz 384 MHz 576 MHz 624MHz Select the highest Cd Clock frequency supported by the platform GT PM Support Enabled Disabled Enable Disable GT PM Support PAVP Enable Enabled Disabled Enable Disable PAVP Memory Scrambler Enabled Disabled Enable Disable Memory Scrambler support Minimum Refresh Rate of 2x Enabling this will double the DRAM refresh rate at the cost of memory bandwidth Required for iTe...

Page 90: ...isable Misc Features 6 9 7 HD Audio Configuration Feature Options Description HD Audio Support Enabled Disabled Control Detection of the Azalia device Disabled Azalia will be unconditionally disabled Enabled Azalia will be unconditionally Enabled Auto Azalia will be enabled if present disabled otherwise HD Audio DSP Enabled Disabled Enable Disable HD Audio DSP HD Audio PME Enabled Disabled Enables...

Page 91: ...HSUART 1 Support D24 F0 Disabled PCI Mode Enable Disable LPSS HSUART 1 Support LPSS HSUART 2 Support D24 F1 Disabled PCI Mode Enable Disable LPSS HSUART 2 Support LPSS IOSF PMCTL S0ix Enable Enable Disable Enable LPSS IOSF Bridge PMCTL Register S0ix Bits LPSS CAM1 I2C Clock Gating Configuration Enable Disable Enable Disable LPSS CAM1 I2C Clock Gating LPSS CAM0 I2C Clock Gating Configuration Enable...

Page 92: ...r Memory write Enable Disable Compliance Mode Enabled Disabled Compliance Mode Enable Disable PCIE Express Root Port 0 3 Submenu Configure PCIE Express Root Port Settings 6 9 10 PCIE Express Root Port 0 3 Feature Options Description PCI Express Root Port x Enabled Disabled Control the PCI Express Root Port ASPM Enabled Disabled PCI Express Active State Power Management settings L1 Substances Disab...

Page 93: ...ENFE Enabled Disabled Enable or disable Root PCI Express System Error on Non Fatal Error SECE Enabled Disabled Root PCI Express System Error on Correctable Error Enable Disable PME SCI Enabled Disabled PCI Express PME SCI Enable Disable Hot Plug Enabled Disabled PCI Express Hot Plug Enable Disable PCIe Speed Auto GEN1 GEN2 Configure PCIe Speed CHV A1 always with Gen1 Speed Transmitter Half Swing E...

Page 94: ... PCH PCIE Disabled Disable override Manual Manually enter override values Auto default Maintain default BIOS flow PCIE LTR Lock Enabled Disabled PCIE LTR Configuration Lock PCIe Selectable De emphasis Enabled Disabled When the Link is operating at 5 0 GT s speed this bit selects the level of de emphasis for an Upstream component 1b 3 5 dB 0b 6 dB ...

Page 95: ...ate Port x Enable Disable Enable or Disable SATA Port SATA Port x Hot Plug Enable Disable If enabled SATA port will be reported as Hot Plug capable Spin Up Device Enable Disable If enabled for any of ports Staggerred Spin Up will be performed and only the drives which have this option enabled will spin up at boot Otherwise all drives spin up at boot 6 9 12 SCC Configuration Feature Options Descrip...

Page 96: ... not be detected by BIOS or OS USB 3 Port 0 3 Enabled Disabled Enable Disable USB port Once disabled any USB devices plug into the connector will not be detected by BIOS or OS XHCI Disable Compliance Mode True False Options to disable XHCI Link Compliance Mode Default is FALSE to not disable Compliance Mode Set TRUE to disable Compliance Mode 6 9 14 Miscellaneous Configuration Feature Options Desc...

Page 97: ...bled Disabled Enable or Disable the Wake on Lan BIOS Lock Enabled Disabled Enable Disable the SC BIOS Lock Enable feature Required to be enabled to ensure SMM protection of flash RTC Lock Enabled Disabled Enable will lock bytes 38h 3Fh in the lower upper 128 byte bank of RTC RAM Flash Protection Range Registers FPRR Enabled Disabled Enable Flash Protection Range Registers ...

Page 98: ...o boot or enter Setup In Setup the User will have Administrator rights 6 10 1 Secure Boot Feature Options Description Secure Boot Enabled Disabled Secure Boot activated when Platform Key PK is enrolled System mode is User Deployed and CSM function is disabled NOTE If Secure Boot will be enabled System Bios is immediately configured without CSM Secure Boot Customization Standard Custom Secure Boot ...

Page 99: ...rce System to User Mode Configure NVRAM to contain OEM defined factory default Secure Boot keys Enroll Efi Image Enter Allow the image to run in Secure Boot mode Enroll SHA256 Hash certificate of a PE image into Authorized Signature Database db Restore DB defaults Enter Restore DB variable to factory defaults Platform Key PK Enter Enroll Factory Default or load certificates from a file 1 Public Ke...

Page 100: ...s Update Append Enroll Factory Default or load certificates from a file 1 Public Key Certificate in a EFI_SIGNATURE_LIST b EFI_CERT_X509 DER encoded c EFI_CERT_RSA2048 bin d EFI_CERT_SHA256 385 512 2 Authenticated UEFI Variable 3 EFI PE COFF Image SHA256 Key Source Factory External Mixed Forbidden Signatures Update Append Enroll Factory Default or load certificates from a file 1 Public Key Certifi...

Page 101: ...I_CERT_RSA2048 bin d EFI_CERT_SHA256 385 512 2 Authenticated UEFI Variable 3 EFI PE COFF Image SHA256 Key Source Factory External Mixed OsRecovery Signatures Update Append Enroll Factory Default or load certificates from a file 1 Public Key Certificate in a EFI_SIGNATURE_LIST b EFI_CERT_X509 DER encoded c EFI_CERT_RSA2048 bin d EFI_CERT_SHA256 385 512 2 Authenticated UEFI Variable 3 EFI PE COFF Im...

Page 102: ...gher priority This can be avoided by filtering UEFI Boot out Boot Priority 2 SATA Port 0 1 USB 2 0 Port 0 7 USB 3 0 Port 0 3 SD Card eMMC Legacy LAN UEFI LAN External Devices Built in Application Define which boot device should have the second highest boot priority Boot Priority 3 SATA Port 0 1 USB 2 0 Port 0 7 USB 3 0 Port 0 3 SD Card eMMC Legacy LAN UEFI LAN External Devices Built in Application...

Page 103: ...ext boot depending on the settings in the Advanced Boot Device Selection Note The number of available Boot options is dependent on the devices which are connected This windows shows the actual configured boot priority list which is set in the Boot Priority options above Note By pressing F10 during POST system will display a Boot Menu for directly booting a selected device Fast Boot Enabled Disable...

Page 104: ...n function will be disabled New Boot Option Policy Default Place First Place Last Controls the placement of newly detected UEFI boot options 6 12 Save Exit The following sections describe each of the options in this menu Save Changes and Exit After making changes in the setup menus always select Exit Saving Changes This procedure stores the selections displayed in the menus in a flash The next tim...

Page 105: ...ons saves all the selections without exiting Setup You can return to the other menus if you want to review and change your selections Discard Changes Discard changes made so far to any of the setup options Restore Defaults Restore load default values for all the setup options Restore User Defaults Restore the User defaults to all the setup options Save as User Defaults Save changes done so far as ...

Page 106: ...lable filesystem devices WARNING This function will still work even if mass storage devices are not registered into the boot device list via MSC BIOS Configuration tool MBconf tool For example only Harddisk is registered as possible boot device and a USB Stick with an EFI shell is plugged the shell can still be executed from the USB Stick with this option ...

Page 107: ...s platform dependent FAT FAT32 EXT3 EXT4 NTFS Image location within file system Recovery FlashImg bin To start the update make sure that the medium with the correct Bios stored is connected and Update Source is set to Local Block Devices In Bios section Main MSC Firmware Update configure control flags as needed Then enter Start firmware Update After Bios update is done system will reboot Update fr...

Page 108: ...rameters Here is an example of a simple txt file which contains the network configuration data ts is loaded by Autflash with the switches net nc Filename e g AutoFlash efi u e net fc configfile txt Network Interface 0 Config Mode DHCP Network Protocol TFTP Server Address Mode static Server Name testserver testnet com File Name Mode manual Image File Name Boot Bios FlashImg bin ...

Page 109: ...d 6 15 Bios Update from Linux It is also possible to trigger the update from Linux Make sure the Image location is within file system Recovery FlashImg bin and the device is inserted as described in 6 13 To start the update from Linux run the AutoFLASH tool as root and probably set the permission for the file with chmod 775 AutoFLASH AutoFLASH u Then reboot system The update will start automatical...

Page 110: ...can happen that the system will not boot In this case it is possible to restore the Bios with the following method 1 Prepare the SPI Image flashimg bin as described in section 6 13 2 Power on the system 3 Bios will search for the file and if found a Bios recovery will be started 4 After Bios recovery is finished the system will perform a powercycle and the system should boot normal again without t...

Page 111: ...ect its own flash to prevent malicious applications from changing the bios code This write protection can only be disabled by a global reset so flash writes can only be done by the bios code itself Hash based checksum checks for bios images Bios images include a hash based checksum to safeguard against file and or memory corruption This hash will be checked before programming a new bios Bios updat...

Page 112: ...ort in a variety of ways With a live system go into setup and enter the Firmware Update submenu If the last line starts with Trusted Update it is supported in this bios version When you load a bios image into the MSC bios editor V2 30 or later bios images with support for Trusted Update will show a tab called Trusted Update Ask your MSC contact if the bios for your platform supports this feature K...

Page 113: ... crt OpenSSL generates keys in a different format therefore some conversion must be done before those keys can be used for Trusted Update However all required conversion can be done with the openssl tool as seen above The important files are the private key file key pfx and the public key certificate key cer Trusted Update key usage MakeCert or OpenSSL will prompt you for a password when generatin...

Page 114: ...private key pfx file and enter the required password into the boxes below 5 Now save your bios image and the bios file will be updated with the provided public key and a signature for Trusted Update will be generated and added to the bios image Example Usage Switching from unsigned to signed updates If your currently running bios has Trusted Update not enable yet you only need to set a public key ...

Page 115: ... NV ROM are invalidated thus forcing the board to start up with default values BIOS Recovery By shorting the pins of this jumper during boot the system is forced into crisis recovery mode For more information see chapter 3 1 6 21 Post Codes For Post Code information please look on the MSC Technologies Support Website or contact Avnet Integrated MSC Technical Support Email support msc technologies ...

Page 116: ... state of the processor The increased clock rate is limited by the processor s power current and thermal limits as well as the number of cores currently in use and the maximum frequency of the active cores For more information about Intel Turbo Boost 2 Technology visit the Intel website Note Turbo Boost will only work if EIST is enabled Reference http en wikipedia org wiki Intel_Turbo_Boost ASPM A...

Page 117: ...ologies offers a complete solution to provide full hardware support for the virtualization of Intel platforms Reference http ark intel com VTList aspx http www intel com technology itj 2006 v10i3 2 io 7 conclusion htm Fast Boot Fast Boot supported by Aptio provides faster boot time by learning the system configuration on the first boot On the Next boot system boots faster because the bios will onl...

Page 118: ...p en wikipedia org wiki Trusted_Platform_Module TXT Trusted Execution Technology Due to the complexity of this feature please visit http www intel com content dam www public us en documents white papers trusted execution technology security paper pdf Note To use this feature VT Vt d SMX and TPM must be enabled 8 EAPI The Embedded Application Programming Interface EAPI used by this module provides ...

Page 119: ...ixed disk int13h device 8xh Solution Check in BIOS setup under Advanced USB Configuration and at the bottom it should have a list of USB mass storage devices Here you can choose between Floppy Forced Floppy Hard Disk or CD ROM behavior of your USB stick Issue 3 SATA 6Gb s SATA 6Gb s behavior is functional only with SATA 6Gb s cable Solution Use SATA 6Gb s cable Issue 4 Windows Installation If Wind...

Page 120: ...ues related to OpenSSL please contact openssl core openssl org OpenSSL License Copyright c 1998 2011 The OpenSSL Project All rights reserved Redistribution and use in source and binary forms with or without modification are permitted provided that the following conditions are met 1 Redistributions of source code must retain the above copyright notice this list of conditions and the following discl...

Page 121: ... permission For written permission please contact openssl core openssl org 5 Products derived from this software may not be called OpenSSL nor may OpenSSL appear in their names without prior written permission of the OpenSSL Project 6 Redistributions of any form whatsoever must retain the following acknowledgment This product includes software developed by the OpenSSL Project for use in the OpenSS...

Page 122: ...LIABILITY OR TORT INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE This product includes cryptographic software written by Eric Young eay cryptsoft com This product includes software written by Tim Hudson tjh cryptsoft com Original SSLeay License Copyright C 1995 1998 Eric Young eay cryptsoft com All rights reser...

Page 123: ...f the parts of the library used This can be in the form of a textual message at program startup or in documentation online or textual provided with the package Redistribution and use in source and binary forms with or without modification are permitted provided that the following conditions are met 1 Redistributions of source code must retain the copyright notice this list of conditions and the fo...

Page 124: ...TICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT INDIRECT INCIDENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENC...

Page 125: ... with or without modification are permitted provided that the following conditions are met 1 Redistributions of source code must retain the above copyright notice this list of conditions and the following disclaimer 2 Redistributions in binary form must reproduce the above copyright notice this list of conditions and the following disclaimer in the documentation and or other materials provided wit...

Page 126: ...ED IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT INDIRECT INCIDENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENCE OR OTHERWISE ARIS...

Page 127: ...licant devel for more information about the design of wpa_supplicant and porting to other drivers One main goal is to add full WPA WPA2 support to Linux wireless extensions to allow new drivers to be supported without having to implement new driver specific interface code in wpa_supplicant WPA The original security mechanism of IEEE 802 11 standard was not designed to be strong and has proven to b...

Page 128: ...ification done by Wi Fi Alliance Wi Fi provides information about WPA at its web site http www wi fi org OpenSection protected_access asp IEEE 802 11 standard defined wired equivalent privacy WEP algorithm for protecting wireless networks WEP uses RC4 with 40 bit keys 24 bit initialization vector IV and CRC32 to protect against packet forgery All these choices have proven to be insufficient key sp...

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