MSC C6B-SLH
MSC C6B-SLH User Manual
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6.9.6 PCI Express Configuration
Feature
Options
Description
PCI Express Clock Gating
Enabled, Disabled
Enable or disable PCI Express Clock Gating for each root port.
Legacy IO Low Latency
Enabled, Disabled
Set to enable low latenc of legacy IO. Some systems require lower
IO latency irrespective of power. This is a tradeoff between power
and IO latency.
DMI Link ASPM Control
Enabled, Disabled
Enable/Disable the control of Active State Power Management on
SA side of the DMI Link
Port8xh Decode
Enabled, Disabled
PCI Express Port8xh Decode Enable/Disable.
Peer Memory Write Enable
Enabled, Disabled
Peer Memory Write Enable/Disable
Compliance Test Mode
Enabled, Disabled
Enable when using Compliance Load Board
PCIe-USB Glitch W/A
Enabled, Disabled
PCIe-USB Glitch W/A for bad USB device(s) connected behind
PCIE/PEG Port.
PCIe function swap
Enabled, Disabled
When Disabled, prevents PCIE rootport function swap. If any
function other than 0th is enabled, 0th will become visible.
PCI Express Gen3 Eq
Parameters
Enabled, Disabled
Submenu
PCIe Root Port 1 (Not
Connected)
Submenu
Submenu
PCIe Root Port 2 (Not
Connected)
Submenu
Submenu
PCIe Root Port 3 (Not
Connected)
Submenu
Submenu
PCIe Root Port 4 (Assigned
to Lan)
Submenu
Submenu
PCIe Root Port 5
(COMExpress lane 4)
Submenu
Submenu
PCIe Root Port 6
(COMExpress lane 5)
Submenu
Submenu