3
Bus Interface
In applications where the expanded-mode is already be-
ing used, it is convenient to use the bus interface to the
HCTL-2020. Figure 2, “Bus Interface Control Signals”, is the
schematic diagram to generate the control signals in the
expanded mode.
The subroutines to read and reset follow.
;******************************************************************************
;THIS SUBROUTINE READS A VALUE FROM THE HCTL-2020. THE HIGH ;BYTE OF DATA IS RE-
TURNED IN REG IY IN THE CORRECT ORDER OF ;HIGH AND LOW BYTES.
;THE TWO BYTES ARE MAPPED AT THE MEMORY LOCATIONS AT 0CFFOh ;AND 0CFFh RE-
SPECTIVELY.
;******************************************************************************
H2020 EQU $0C000
RD2020: LDY H2020
RTS
;******************************************************************************
;THIS SUBROUTINE IS USED TO RESET THE HCTL-2020. THE RESET ;SIGNAL IS MAPPED TO
MEMORY LOCATION 0CFF2h.
;******************************************************************************
REST2020 EQU $0CFF2
RST2020:
PSHA
LDAA REST2020 ;READ LOCATION $CFF2 TO CAUSE RESET
PULA
RTS
