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AC4830xC-C Data Book

General

Revision 1.0

1

March 2000

About this Data Book

Purpose and Scope

This Data Book describes the hardware and timing characteristics, applications and use
of the AC4830xC-C VoPP, Voice over Packet Processors, from AudioCodes Ltd. It is
designed for reading by any regular User without specialist skills but familiar with the
applications, products and services of AudioCodes Ltd.

Structure of this Manual

The Data Book has the following sections, which will help you to find the information
you need:

For Information on:

Look at Chapter:

Release Notes, Notices and Warranty

General

Contents, Figures and Tables

Contents

Overview and Features

1. Introduction

The Interfaces of the AC4830xC-C

2. Functional Interfaces

Specification of the AC4830xC-C.

3. Chip Data and Timing

Applications, Evaluation System and Testing

4. Application Notes

PCM Highway Interface

5. PCM Highway Interface

Full Index of the Data Book

Index

Abbreviations and Terminology

Each abbreviation, unless widely used, is spelled out in full when first used, and only
Industry standard terms are used throughout this manual. The $ symbol indicates
hexadecimal notation.

Data Book Revision 1.0 - Release Note

This Data Book describes the latest

Hardware

and timing specifications for the

AC4830xC-C. The

Software

specifications are described in “AC4830xC-C Designer’s

Manual”, Catalog Number LTRT-00066.

Acknowledgements

NetFax

®

and NetCoder

®

are registered by AudioCodes Ltd.

AudioCodes acknowledges that various products referred to in this manual are subject
to copyright and/or trademark by their respective registered holders.

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Summary of Contents for AC4830 C-C Series

Page 1: ...577 0488 Fax 408 577 0492 International AudioCodes Ltd 4 HaHoresh Rd PO Box 14 Yehud 56470 Israel Tel 972 3 539 4000 Fax 972 3 539 4061 Technical Support support audiocodes com AC4830xC C VoPP Voice...

Page 2: ......

Page 3: ...C4830xC C 2 Functional Interfaces Specification of the AC4830xC C 3 Chip Data and Timing Applications Evaluation System and Testing 4 Application Notes PCM Highway Interface 5 PCM Highway Interface Fu...

Page 4: ...l be at AudioCodes discretion to replace the non conforming Products or issue the Buyer credit for the purchase price of the non conforming Products where within the warranty period 1 AudioCodes has r...

Page 5: ...32 3 2 1 Absolute Maximum Ratings over Specified Temp Range 32 3 2 2 Electrical Characteristics 34 3 3 Timing Characteristics 35 3 3 1 Memory and I O Interface Timing 35 3 3 1 1 Memory Read 35 3 3 1...

Page 6: ...odes Ltd AC4830xC C VoPP 4 Catalog Number LTRT 00060 4 1 Interface Application Using PCM Framer Codec 53 54 4 2 Interface Application Using Codec 55 5 PCM Highway Interface 57 5 1 E1 PCM Highway 57 In...

Page 7: ...ory Read Timing 36 Figure 3 2 Memory Write Timing 37 Figure 3 3 I O Read Timing 38 Figure 3 4 I O Write Timing 39 Figure 3 5 PCM Port Receive Timing Requirements using Codec 41 Figure 3 6 PCM Port Tra...

Page 8: ...iming Requirements 37 Table 3 6 I O Read Timing Parameters 38 Table 3 7 I O Write Timing Parameters 39 Table 3 8 PCM Port Receive Timing Requirements using Codec 40 Table 3 9 PCM Port Transmit Switchi...

Page 9: ...voice compression and fax relay functions for one or two independent voice and fax channels There are currently two members of the AC4830xC C family AC48302C C dual channels for client applications AC...

Page 10: ...tion and detection Automatic switching to PCM or ADPCM upon fax data detection G 168 compliant 25 ms length adaptive Echo Canceler High performance Voice Activity Detector VAD and Comfort Noise Genera...

Page 11: ...gth ms 25 25 DTMF TIA 464B MF R1 MF R2 SS 4 SS 5 AC15 Call progress User defined Bellcore Std Caller ID generation detection CAS E M signaling Input and output gain control G3 Fax relay T 38 compliant...

Page 12: ...AudioCodes Ltd AC4830xC C VoPP 10 Catalog Number LTRT 00060 Reader s Notes...

Page 13: ...4830xC C performs receive and transmit operations simultaneously It receives compressed packetized speech data from a remote AC4830xC C unit through the Host Port Interface It decompresses speech data...

Page 14: ...ax Data Discriminator MUX G3 FAX Relay 2400 14400 bps Baseband Processing Voice Compression Voice NetCoder 6 4 9 6 kbps G 711 PCM 64 kbps G 727 E ADPCM 16 40 kbps G 726 ADPCM 16 40 kbps G 723 1 MP MLQ...

Page 15: ...es are shown below in Figure 2 2 and are described individually in the following pages Figure 2 2 AC4830xC C Interface Diagram Host Port Interface HOST Memory I O Interface R W MS Data Address 16 bit...

Page 16: ...MOUT PCMCLK is a 2 048 MHz clock that can be generated internally from the AC4830xC C or externally from a codec PCMFS is the PCM Frame Sync that is generated every 125 sec to comply with the E1 trans...

Page 17: ...PCM Clock and the Frame Sync characteristics The setting of the AC4830xC C working clock is made by modifying the PLLMUL field of the last word of the Kernel File which is the PLLMUL Register as show...

Page 18: ...ble 2 1 External Crystal Examples Crystal Frequency MHz PLLMUL CLKOUT MHz Source for 2 048 MHz Notes 20 4 100 Do Not Use Default Value in Kernel File 25 3 100 Do Not Use See Section 3 3 1 on page 35 1...

Page 19: ...C expects all transfers to consist of two consecutive bytes A dedicated pin HI LO indicates whether the first or second byte is being transferred Two control pins HRS0 and HRS1 control Host access to...

Page 20: ...s data buses a data strobe and either one read write strobe or two separate strobes for read and write An HPI ready pin HRDY is provided for Hosts that support an asynchronous input to insert wait sta...

Page 21: ...D15 IOS SIGEN MEMORY I O Interface VOICE Interface TAP A A 1 2 2 1 B B CAS E M Port The AC4830xC C handles E M signals through an external I O CAS E M port by means of I O strobe IOS read write R W an...

Page 22: ...ating a typical design of an I O port Figure 4 2 on page 56 shows a typical Interface Application when the clock is supplied from the codec illustrating a typical design of an I O port Note It is stro...

Page 23: ...naling The CAS Port signals are shown in Figure 2 7 below Figure 2 7 AC4830xC C CAS Port Interface The low nibble 4 bit sub field of the signaling sample contains the E M AB signaling where the B bit...

Page 24: ...ling bit is in use E M A signaling A1 corresponds to Channel 1 and A2 corresponds to Channel 2 E M AB signaling When two signaling bits are in use E M AB signaling A1 and B1 are both allocated to Chan...

Page 25: ...ster is shifted out of TDO on falling edge of TCK TDO is in high impedance state except when the scanning of data is in progress TMS Test Mode Select Serial control input is clocked into the Test Acce...

Page 26: ...al procedure Kernel download mode BOOT Program download mode Run time packet exchange Figure 2 10 AC4830xC C HPI Memory Map 17FFh HPIA HD 0 to 7 HINT HRDY HAS HCS HRW HRD HWR HRS0 HRS1 HI LO HPIC HPID...

Page 27: ...2 4 Pin Description 2 4 1 Signals and Pin out 144 pin TQFP package Table 2 3 AC4830xC C Signals and Pin out TQFP Package continues on 6 pages VoPNP Name TQFP Pin I O Description PCMIN 45 I PCM data i...

Page 28: ...from the Host port interface Hosts must drive HR W low to write to the Host port interface Hosts without an R W strobe must use an address line HRD 127 I Host Read The active low internal signal is t...

Page 29: ...atched on the HRD or HWR falling edge when HAS stays high HRS0 39 I Host register select 0 HRS1 46 I Host register select 1 HPISEL 31 I Host Port Interface select Must be connected to GNDI For future...

Page 30: ...rnal RAM Data 4 D5 104 I O Z External RAM Data 5 D6 113 I O Z External RAM Data 6 D7 114 I O Z External RAM Data 7 D8 115 I O Z External RAM Data 8 D9 116 I O Z External RAM Data 9 D10 117 I O Z Exter...

Page 31: ...ress 13 A14 10 O External RAM Address 14 A15 11 O External RAM Address 15 Must not be connected A16 105 O External RAM Address 16 Connect to A15 of SRAM RSRV1 19 I Must be connected to 3 3 V RSRV2 30...

Page 32: ...up through a 4 7k resistor to 3 3 V RSRV19 92 I Must be connected to 3 3 V RSRV20 66 I Connect externally to HINT and pull up thru 4 7k resistor RSRV21 48 I Must be connected externally to PCMCLK RSRV...

Page 33: ...pport V 17 V 21 V 27ter V 29 V 33 Voice fax Switching Automatic Echo Cancelation G 168 Max echo path 25 ms DTMF Detection and Generation Detection Resolution 10 ms Generation Resolution 1 ms 16 digits...

Page 34: ...Specified Temp Range Supply voltage range VDDI 0 3 to 4 0 V Supply voltage range VDDC 0 3 to 2 0 V Input voltage range 0 3 to 4 5 V Output voltage range 0 3 to 4 5 V Operating case temperature range...

Page 35: ...GND 0 V RESET RSRV20 XIN PCMCLK TCLKR RSRV21 TCLKX HCS HRD HWR TDI TMS RSRV11 RSRV13 CLKMD2 2 2 VDDI 0 3 TCK TRST 2 5 VDDI 0 3 VIH High level input voltage VDDI 3 3 0 3 V All other inputs 2 VDDI 0 3 V...

Page 36: ...0 HD 7 0 Bus holders enabled VDDI MAX VI VSS to VDDI 175 175 IIZ Input current for outputs in high impedance All other inputs VDDI MAX VO VSS to VDDI 5 5 A EXTCLK 40 40 TRST With internal pulldown 5 3...

Page 37: ...ow from CLKOUT low 1 3 19 Delay time MS high from CLKOUT low 1 3 12 Hold time address valid after CLKOUT low 2 3 13 Access time read data access from address valid 3u 18 Access time read data access f...

Page 38: ...or a 16 384 MHz clock 1 tc CI 1 16 384 nsec 61 nsec 2 tc CO 61 6 nsec 10 166 nsec 3 H 0 5 tc CO 5 083 nsec 4 The true value of 13 is 2H 7 3 166 nsec and 18 is 2H 8 2 166 nsec Figure 3 1 Memory Read Ti...

Page 39: ...ata valid from CLKOUT low 0 6 29 Delay time MS high from CLKOUT low 1 3 30 Delay time R W low from CLKOUT high 1 3 33 Delay time R W high from CLKOUT high 1 3 31 Delay time MS low after R W low H 2 H...

Page 40: ...e read data access from IOS low 2H 7 43 Setup time read data before CLKOUT high 6 45 Delay time address valid from CLKOUT low 2 3 46 Delay time IOS low from CLKOUT high 2 3 47 Delay time IOS high from...

Page 41: ...Delay time write data valid from CLKOUT high H 5 H 8 47 Delay time IOS high from CLKOUT high 2 3 52 Delay time R W low from CLKOUT low 1 3 53 Delay time R W high from CLKOUT low 1 3 54 Hold time addre...

Page 42: ...M port clock 4883 4883 62 Fall time PCM port clock 8 63 Rise time PCM port clock 8 64 Pulse duration PCM port clock low high 59 65 Setup time PCMFS before PCMCLK falling edge 1 66 Hold time PCMFS afte...

Page 43: ...dec Parameter units ns Min Max 71 Disable time PCMOUT after PCMCLK rising 1 4 72 Enable time PCMOUT after PCMCLK rising 0 7 73 Hold time PCMOUT valid after PCMCLK rising 0 7 Values are derived from ch...

Page 44: ...AudioCodes Ltd AC4830xC C VoPP 42 Catalog Number LTRT 00060 Figure 3 6 PCM Port Transmit Timing Requirements using Codec 72 PCMFS INT PCMCLK PCMOUT 73 64 64 61 71...

Page 45: ...PCM Framer Parameter units ns Min Max 61 Cycle time PCM port clock 1223 62 Fall time PCM port clock 8 63 Rise time PCM port clock 8 64 Pulse duration PCM port clock low high 37 65 Setup time PCMFS be...

Page 46: ...LK rising 3 11 Values are derived from characterization data but not tested Table 3 13 PCM Port Transmit Timing using PCM Framer Parameter units ns Min Max 61 Cycle time PCM port clock 122 62 Fall tim...

Page 47: ...cond byte 5 20 84 Delay time HCDS high to HRDY high CLKOUT 100 MHz 60 85 Setup time HD valid before HRDY rising edge CLKOUT 100 MHz 5 86 Hold time HD valid after HCDS rising edge 0 12 87 Delay time CL...

Page 48: ...ase 1 when using HRDY see Figure 3 11 50 case 2 without using HRDY see Figure 3 9 Figure 3 10 50 97 Setup time HD valid before HCDS rising edge 12 98 Hold time HD valid after HCDS rising edge 3 When t...

Page 49: ...AC4830xC C Data Book Chapter 3 Chip Data and Timing Revision 1 0 47 March 2000 Figure 3 9 Read Write Access Without HRDY or HAS Valid Valid Valid Valid...

Page 50: ...AudioCodes Ltd AC4830xC C VoPP 48 Catalog Number LTRT 00060 Figure 3 10 Read Write Access Using HAS Without HRDY...

Page 51: ...AC4830xC C Data Book Chapter 3 Chip Data and Timing Revision 1 0 49 March 2000 Figure 3 11 Read Write Access with HRDY VALID VALID VALID VALID...

Page 52: ...eter units ns Min Max 101 Hold time RESET after CLKOUT low 0 102 Pulse duration RESET low 1 During Kernel Download Mode CLKOUT 10 MHz 2052 During Other Modes CLKOUT 100 MHz 252 103 Setup time RESET be...

Page 53: ...examples being shown in Table 2 1 on page 16 Please follow the guidelines for selecting the crystal value as explained in section 2 2 2 on page 15 Connecting the selected crystal across XOUT and XIN e...

Page 54: ...s packaged in a 144 pin TQFP 20x20 mm body shown below Figure 3 15 TQFP Packaging Specifications Notes 1 All linear dimensions are in millimeters 2 This drawing is subject to change without notice 3 F...

Page 55: ...pter 4 Applications Revision 1 0 53 March 2000 4 APPLICATIONS 4 1 Interface Application Using PCM Framer Codec Figure 4 1 on page 52 shows a typical Interface Application when the clock is supplied fr...

Page 56: ...AudioCodes Ltd AC4830xC C VoPP 54 Catalog Number LTRT 00060 Figure 4 1 Interface Application External PCM Clocks...

Page 57: ...0xC C Data Book Chapter 4 Applications Revision 1 0 55 March 2000 4 2 Interface Application Using Codec Figure 4 2 on page 54 shows a typical Interface Application when the clock is supplied from the...

Page 58: ...AudioCodes Ltd AC4830xC C VoPP 56 Catalog Number LTRT 00060 Figure 4 2 Interface Application Driving a Codec...

Page 59: ...CHANNEL 31 TIMESLOT 30 CHANNEL 32 TIMESLOT 31 CHANNEL 1 TIMESLOT 0 PCMOUT MSB LSB MSB LSB It should be noted that in the above case PCMFS appears only in the 127th time slot When working with more th...

Page 60: ...AudioCodes Ltd AC4830xC C VoPP 58 Catalog Number LTRT 00060 Reader s Notes...

Page 61: ...8 39 45 46 50 CLKP Clock Polarity field 40 43 CNG Comfort Noise Generator field 11 31 Co Output Capacitance 34 Control Pins 17 Current Consumption 32 Cycle Time 40 41 43 44 46 Data 23 28 34 Data Bus L...

Page 62: ...27 45 46 HRDY Host Ready Signal 18 26 45 46 47 48 49 50 HRDY HPI Ready Pin 18 HRS0 Host Register Select 0 Signal 17 25 27 45 46 HRS1 Host Register Select 1 Signal 17 25 27 45 46 HWR Host Write Signal...

Page 63: ...N PCM Data Input Signal 25 40 43 PCMOUT PCM Data Output Signal 25 41 44 Pin Description 25 Power Supply 32 Pulse Duration 37 40 41 43 44 46 50 R W Memory Read Write Signal 18 19 26 27 37 39 47 48 49 R...

Page 64: ...field 11 31 VAD Response Time 31 VDDC 30 32 33 VDDI 26 27 29 30 32 33 34 VIH High level Input Voltage 33 VIL Low level Input Voltage 33 VOH High Level Output Voltage 34 Voice Coders 31 Voice Packetiz...

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