Atmel XMEGA B, User Manual

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204 XMEGA B [DATASHEET]
8291B–AVR–01/2013
17.3.3 INTCTRL – Interrupt Control register

Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.

Bit 3:2 – COMPINTLVL[1:0]: Compare Match Interrupt Enable
These bits enable the RTC compare match interrupt and select the interrupt level, as described in “Interrupts and
Programmable Multilevel Interrupt Controller” on page 118 . The enabled interrupt will trigger when COMPIF in the
INTFLAGS register is set.

Bit 1:0 – OVFINTLVL[1:0]: Overflow Interrupt Enable
These bits enable the RTC overflow interrupt and select the interrupt level, as described in “Interrupts and Programmable
Multilevel Interrupt Controller” on page 118 . The enabled interrupt will trigger when OVFIF in the INTFLAGS register is
set.
17.3.4 INTFLAGS
–
Interrupt Flag register
 Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.

Bit 1 – COMPIF: Compare Match Interrupt Flag
This flag is set on the next count after a compare match condition occurs. It is cleared automatically when the RTC
compare match interrupt vector is executed. The flag can also be cleared by writing a one to its bit location.

Bit 0 – OVFIF: Overflow Interrupt Flag
This flag is set on the next count after an overflow condition occurs. It is cleared automatically when the RTC overflow
interrupt vector is executed. The flag can also be cleared by writing a one to its bit location.
Bit 7 6 5 4 3 2 1 0
+0x02
– – – – COMPINTLVL[1:0] OVFINTLVL[1:0]
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
+0x03
– – – – – – COMPIF OVFIF
Read/Write R R R R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0