Atmel XMEGA B, User Manual

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155 XMEGA B [DATASHEET]
8291B–AVR–01/2013
Figure 13-4. Period and compare double buffering.
When the CC channels are used for a capture operation, a similar double buffering mechanism is used, but in this case
the buffer valid flag is set on the capture event, as shown in
Figure 13-5 . For capture, the buffer register and the
corresponding CCx register act like a FIFO. When the CC register is empty or read, any content in the buffer register is
passed to the CC register. The buffer valid flag is passed to set the CCx interrupt flag (IF) and generate the optional
interrupt.
Figure 13-5. Capture double buffering.
Both the CCx and CCxBUF registers are available as an I/O register. This allows initialization and bypassing of the buffer
register and the double buffering function.
13.6 Counter Operation
Depending on the mode of operation, the counter is cleared, reloaded, incremented, or decremented at each
timer/counter clock input.
13.6.1 Normal Operation
In normal operation, the counter will count in the direction set by the direction (DIR) bit for each clock until it reaches TOP
or BOTTOM. When up-counting and TOP is reached, the counter will be set to zero when the next clock is given. When
down-counting, the counter is reloaded with the period register value when BOTTOM is reached.
BV
UPDATE
"write enable"
"data write"
=
CNT
"match"
CCxBUF
CCx
EN
EN
BV
"capture"
IF
CNT
CCxBUF
CCx
EN
EN
"INT/DMA
request"
data read