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Ref.:

UoD_SpW-10X_

UserManual

Issue:

3.4

SpW-10X

SpaceWire Router

User Manual

Date:

11

th

July 2008

Preliminary

87

dependent on the previous input port which had access to that output port. The next input port to
transfer data to an output port is the next highest port number (modulo number of ports) that has data
to send. Thus the input port which previously had access to the output port will be selected last by the
router control logic. For example, if input port 2 is transferring data to output port 1 and input ports 5
and 7 are waiting to transfer data to port 1, then port 5 will selected next.

Packets which have high priority are always selected before low priority packets in the router. If two or
more packets of the same priority level are attempting to use the same destination port then the
packets are arbitrated in a fair manner.

Note that router configuration packets, both commands and replies, are treated the same as any other
packet as far as arbitration is concerned. The arbitration scheme is equally applicable to all types of
packets with no exceptions. When sending long packets, arbitration can cause substantial delays in
transferring information.

The following sub-sections illustrate the various scenarios where arbitration is necessary.

8.3.2.1 Arbitration of packets with matching priority (1)

In the Figure 8-6 an example of arbitrating between packets with the same priority is illustrated. Only
router ports 1-5 are shown for clarity.

At stage one input ports 1 and 3 have packets to be routed to output port 5. The previous input port to
use output port 5 was input port 3 therefore the next input port to be selected by output port 5 will be
input port 1 (assuming input ports 6, 7, 8, 9, 10 and 0 are not requesting to use output port 5).

At stage two the router selects the packet arriving at input port 1 and the packet is routed through
output port 5. Input port 3 waits until all of the packet from input port 1 has been transferred.

At stage three the complete packet has been transferred from input port 1. Now input port 3 is able to
transfer its packet to output port 5.

R1

2

5

1

3

5

4

5

R1

2

5

1

3

5

4

Two packets waiting to use port 5

(Previous port which accessed port 5 = 3)

Packet from port 1 is selected

R1

2

5

1

3

4

Packet from port 1 completes
Packet from port 3 is selected

R1

2

5

1

3

4

Packet from port 3 is completes

1

2

3

4

Figure 8-6 Arbitration of two packets with matching priority.

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Summary of Contents for SpaceWire Router SpW-10X

Page 1: ... SpaceWire Router User Manual Ref UoD_SpW 10X_UserManual Atmel Part No AT7910E Document Revision Issue 3 4 Date 11th July 2008 Prepared by Chris McClements University of Dundee Steve Parkes University of Dundee Gerald Kempf Austrian Aerospace Checked by Steve Parkes University of Dundee ESA Manager Pierre Fabry ESTEC ...

Page 2: ...Clements 18th August 2006 Issue 2 0 Editorial changes and clarifications Steve Parkes 3rd July 2007 Issue 2 1 Added sections on ASIC pin placement ASIC power consumption bias resistors phase locked loop and anomalies Chris McClements Steve Parkes 28th September 2007 Issue 2 2 Modifications before handed to Atmel Chris McClements Gerald Kempf 4th October 2007 Issue 2 3 Modifications to SpaceWire si...

Page 3: ...g information added VCO bias resistor value corrected Section 5 7 4 Tri state mode changed to deactivate mode Description for time code flag mode bit added Reliability information added Anomaly 2 resolved Details and workarounds for reset anomaly provided Steve Parkes 30th April 2008 Issue 3 3 RD 3 changed Editorial corrections Correction to reset value of GAR table entry Correction to support ema...

Page 4: ...RFACE 17 2 3 EMBEDDED ROUTER 17 2 4 EXPANDING THE NUMBER OF ROUTER PORTS 18 3 FUNCTIONAL OVERVIEW 21 3 1 SPACEWIRE PORTS 22 3 2 EXTERNAL PORTS 22 3 3 CONFIGURATION PORT 23 3 4 ROUTING TABLE 23 3 5 ROUTING CONTROL LOGIC AND CROSSBAR 23 3 6 TIME CODE PROCESSING 24 3 7 CONTROL STATUS REGISTERS 24 4 PIN LOCATIONS 25 5 DEVICE INTERFACE 31 5 1 GLOBAL SIGNALS 31 5 2 SPACEWIRE SIGNALS 32 5 2 1 SpW 10X Spa...

Page 5: ...US INTERFACE OPERATION 49 6 4 RESET CONFIGURATION INTERFACE OPERATION 51 7 SPACEWIRE ROUTER PACKET TYPES 52 7 1 PACKET ADDRESSES 52 7 2 PACKET PRIORITY 53 7 3 PACKET HEADER DELETION 53 7 4 INVALID ADDRESSES 54 7 5 DATA PACKETS 55 7 6 COMMAND PACKETS 55 7 6 1 Supported Commands 55 7 6 2 Read Command 56 7 6 3 Read Incrementing Command 60 7 6 4 Read Modify Write Command 65 7 6 5 Write Command 70 7 6 ...

Page 6: ...roup Adaptive Routing 92 8 3 3 1 Normal Group adaptive routing 92 8 3 3 2 Group adaptive routing when busy 92 8 3 3 3 Group adaptive routing when ports not ready 93 8 3 4 Loop back with Self Addressing 93 8 3 5 Packet Blocking 95 8 3 5 1 Blocked destination 95 8 3 5 2 Stalled source 98 8 3 5 3 Waiting for an output port 101 9 REGISTER DEFINITIONS 103 9 1 INTERNAL MEMORY MAP 103 9 2 REGISTER ADDRES...

Page 7: ...TIMING PARAMETERS 128 10 3 EXTERNAL PORT TIMING PARAMETERS 129 10 4 TIME CODE INTERFACE TIMING PARAMETERS 130 10 5 ERROR STATUS INTERFACE TIMING PARAMETERS 131 10 6 LATENCY AND JITTER 133 10 6 1 Clock Periods 133 10 6 2 Switching Latency 133 10 6 3 Router Latency 133 10 6 4 Time code Latency 134 10 6 5 Time code Jitter 135 10 6 6 200M bits s Input and Output Bit Rate Example 135 11 ELECTRICAL CHAR...

Page 8: ... ERROR ANOMALY 148 13 4 1 Parity Error Action 148 13 4 2 Parity Error Anomaly 148 13 4 3 Parity Error Workaround 149 14 TECHNICAL SUPPORT 150 15 DOCUMENT CHANGES 151 15 1 ISSUE 3 3 TO ISSUE 3 4 151 15 2 ISSUE 3 2 TO ISSUE 3 3 151 15 3 ISSUE 3 1 TO ISSUE 3 2 151 15 4 ISSUE 3 0 TO ISSUE 3 1 152 15 5 ISSUE 2 5 TO ISSUE 3 0 152 15 6 ISSUE 2 4 TO ISSUE 2 5 153 15 7 ISSUE 2 3 TO ISSUE 2 4 153 15 8 ISSUE...

Page 9: ... UoD_SpW 10X_ UserManual Issue 3 4 SpW 10X SpaceWire Router User Manual Date 11th July 2008 Preliminary 9 15 16 ISSUE 1 2 TO ISSUE 1 3 154 15 17 ISSUE 1 1 TO ISSUE 1 2 155 15 18 ISSUE 1 0 TO ISSUE 1 1 155 ...

Page 10: ...GURE 7 2 COMMAND PACKET FORMAT 55 FIGURE 7 3 READ SINGLE ADDRESS COMMAND FORMAT 57 FIGURE 7 4 READ SINGLE ADDRESS REPLY PACKET FORMAT 59 FIGURE 7 5 READ INCREMENTING ADDRESS COMMAND FORMAT 62 FIGURE 7 6 READ INCREMENTING ADDRESS REPLY PACKET FORMAT 64 FIGURE 7 7 READ MODIFY WRITE COMMAND PACKET FORMAT 66 FIGURE 7 8 READ MODIFY WRITE EXAMPLE OPERATION 68 FIGURE 7 9 READ MODIFY WRITE REPLY PACKET FO...

Page 11: ...IGURE 8 26 SOURCE NODE STALLED WATCHDOG MODE B 100 FIGURE 8 27 SOURCE NODE STALLED WATCHDOG MODE C 100 FIGURE 8 28 SOURCE NODE STALLED WATCHDOG MODE D 100 FIGURE 9 1 ROUTER INTERNAL MEMORY MAP 103 FIGURE 9 2 GAR REGISTER FIELDS 105 FIGURE 9 3 SPACEWIRE PORT CONTROL STATUS REGISTER FIELDS 112 FIGURE 9 4 NETWORK DISCOVERY REGISTER FIELDS 116 FIGURE 9 5 ROUTER CONTROL REGISTER FIELDS 117 FIGURE 9 6 E...

Page 12: ...SINGLE ADDRESS CHARACTERISTICS 57 TABLE 7 6 READ SINGLE ADDRESS COMMAND PACKET FIELDS 58 TABLE 7 7 READ SINGLE ADDRESS REPLY PACKET FIELDS 59 TABLE 7 8 READ INCREMENTING ADDRESS CHARACTERISTICS 61 TABLE 7 9 READ INCREMENTING ADDRESS COMMAND PACKET FIELDS 62 TABLE 7 10 READ INCREMENTING ADDRESS REPLY PACKET FIELDS 64 TABLE 7 11 READ MODIFY WRITE COMMAND CHARACTERISTICS 65 TABLE 7 12 READ MODIFY WRI...

Page 13: ...ABLE 9 13 DEVICE MANUFACTURER AND CHIP ID REGISTER FIELDS 122 TABLE 9 14 TIME CODE ENABLE REGISTER FIELDS 124 TABLE 9 15 TRANSMIT CLOCK CONTROL REGISTER BITS 126 TABLE 9 16 DESTINATION KEY REGISTER 127 TABLE 10 1 CLOCK AND RESET TIMING PARAMETERS 128 TABLE 10 2 SERIAL SIGNAL TIMING PARAMETERS 129 TABLE 10 3 EXTERNAL PORT TIMING PARAMETERS 130 TABLE 10 4 TIME CODE INTERFACE TIMING PARAMETERS 131 TA...

Page 14: ...ment CLK Clock Input clock to the SpaceWire router CRC Cyclic Redundancy Check DC Direct Current ECSS European Cooperation for Space Standarization EEP Error end of packet used to denote an error occurred during packet transfer EOP End of packet used to denote a normal end of packet in SpaceWire FIFO First in First out buffer used to transfer data between logic FPGA Field Programmable Gate Array G...

Page 15: ...nd networks AD2 ECSS E50 11A SpaceWire Remote Memory Access Protocol AD3 TBD SpW_10X Standard Microcircuit Drawing Table 1 2 Reference Documents REF Document Number Document Title RD1 LVDS Owner s Manual National Semiconductor Downloadable from http www national com appinfo lvds files National_ LVDS_Owners_Manual_4th_Edition_2008 pdf RD2 AN 1194 Application Note AN 1194 Failsafe Biasing of LVDS In...

Page 16: ... tables etc may be done by sending SpaceWire packets containing configuration commands to the router Instrument 1 Instrument 2 Instrument 3 Instrument 4 Memory Unit Processor SpW 10X Router SpaceWire Links Figure 2 1 Stand Alone Router In Figure 2 1 an example of use of the SpW 10X device as a stand alone router is illustrated There are four instruments connected to the SpW 10X device along with a...

Page 17: ... Active SpaceWire Links Disabled SpaceWire Links SpaceWire Node Figure 2 2 Node Interface In Figure 2 2 a SpW 10X router is used as an interface to a user FPGA or processor which may be part of a SpaceWire enabled instrument control processor or other sub system The interface to the user FPGA or processor is via the external FIFO ports of the SpW 10X router Only three SpaceWire links are needed fo...

Page 18: ...router using the external FIFO ports saving some SpaceWire ports for connecting to additional instruments For redundancy a pair of the SpaceWire nodes with embedded routers may be used 2 4 EXPANDING THE NUMBER OF ROUTER PORTS If a routing switch with a larger number of SpaceWire or external ports is required then this can be accomplished by joining together two or more routers using some of the Sp...

Page 19: ... routers connected together using the external FIFO ports to provide a 16 port router A small amount of external logic is required to connect the external FIFO ports in this way Note that the bandwidth between the two SpW 10X devices is limited by the two external FIFO ports used to interconnect them Each FIFO port can handle one SpaceWire packet at a time in each direction SpW 10X Router SpW 10X ...

Page 20: ...ding the number of SpaceWire Ports 2 Figure 2 5 shows two SpW 10X router devices interconnected using two of the SpaceWire ports on each router This leaves twelve SpaceWire ports for connection to other SpaceWire nodes The External FIFO ports of each router are used to connect to user logic in an FPGA or to a processing device ...

Page 21: ...ossbar switch connecting any input port to any output port An internal configuration port accessible via the crossbar switch from the external parallel input output port or the SpaceWire input output ports A routing table accessible via the configuration port which holds the logical address to output port mapping Control logic to control the operation of the switch performing arbitration and group...

Page 22: ...r has eight bi directional SpaceWire links each conformant with the SpaceWire standard Each SpaceWire link is controlled by an associated link register and routing control logic Network level error recovery is performed when an error is detected on the SpaceWire link as defined in the SpaceWire standard Packets received on SpaceWire links are routed by the routing control logic to the configuratio...

Page 23: ... A group of destination ports can be set in each routing table location to enable group adaptive routing In group adaptive routing a packet can be routed to its destination through one of a set of output ports dependent on which ports in the set are free to use When a packet is received with a logical address the routing table is checked by the routing control logic and the packet is routed to the...

Page 24: ...eWire routing causing time codes to be propagated through the network Two modes of time master operation are supported an automatic mode where a time code is propagated on each external tick in and a normal mode where the time code is propagated dependent on the external time in signal In time code slave mode a valid received time code one plus the value of the router time code register causes a t...

Page 25: ... LVDS reference PO44F 4x driving strength output fast minimum slew rate control PO22F tri 2x driving strength output with tristate fast minimum slew rate control Pin Signal Type Description 1 VDDB 3V3 Power 2 CLK PIC System clock 3 RSTN PIC Reset 4 TestIOEn PIC PRD4 Chip test pin 5 TestEn PIC PRD4 Chip test pin 6 FEEDBDIV 0 PIC PRD4 PLL divider bit 0 LS 7 VSSA1 GND Ground 8 VDDA1 3V3 Power 9 FEEDB...

Page 26: ...ZPB SpW port 2 output data 34 DOUTPlus 2 PFOLVDS33ZP SpW port 2 output data 35 DINPlus 3 PFILVDSZP SpW port 3 input data 36 DINMinus 3 PFILVDSZPB SpW port 3 input data 37 SINPlus 3 PFILVDSZP SpW port 3 input strobe 38 SINMinus 3 PFILVDSZPB SpW port 3 input strobe 39 SOUTMinus 3 PFOLVDS33ZPB SpW port 3 output strobe 40 SOUTPlus 3 PFOLVDS33ZP SpW port 3 output strobe 41 VSSB GND Ground 42 VSSA2 GND ...

Page 27: ...robe 75 SOUTPlus 6 PFOLVDS33ZP SpW port 6 output strobe 76 DOUTMinus 6 PFOLVDS33ZPB SpW port 6 output data 77 DOUTPlus 6 PFOLVDS33ZP SpW port 6 output data 78 DINPlus 7 PFILVDSZP SpW port 7 input data 79 DINMinus 7 PFILVDSZPB SpW port 7 input data 80 SINPlus 7 PFILVDSZP SpW port 7 input strobe 81 SINMinus 7 PFILVDSZPB SpW port 7 input strobe 82 SOUTMinus 7 PFOLVDS33ZPB SpW port 7 output strobe 83 ...

Page 28: ...9 input data 116 EXTINDATA9 1 PIC External FIFO port 9 input data 117 EXTINDATA9 2 PIC External FIFO port 9 input data 118 EXTINDATA9 3 PIC External FIFO port 9 input data 119 EXTINDATA9 4 PIC External FIFO port 9 input data 120 EXTINDATA9 5 PIC External FIFO port 9 input data 121 EXTINDATA9 6 PIC External FIFO port 9 input data 122 EXTINDATA9 7 PIC External FIFO port 9 input data 123 EXTINDATA9 8...

Page 29: ...NDATA10 8 PIC External FIFO port 10 input data 152 EXTINFULLN10 PO44F External FIFO port 10 input full 153 EXTINWRITEN10 PIC External FIFO port 10 input wrte 154 VSSA7 GND Ground 155 VDDA7 3V3 Power 156 VSSB GND Ground 157 VDDB 3V3 Power 158 EXTTICKIN PIC Time code tick in 159 EXTTIMEIN 0 PIC Time code input 160 EXTTIMEIN 1 PIC Time code input 161 EXTTIMEIN 2 PIC Time code input 162 EXTTIMEIN 3 PI...

Page 30: ...4 VSSB GND Ground 185 VDDB 3V3 Power 186 STATMUXOUT 0 PO22F tri PIC Status output configuration input 187 STATMUXOUT 1 PO22F tri PIC Status output configuration input 188 STATMUXOUT 2 PO22F tri PIC Status output configuration input 189 VSSA8 GND Ground 190 VDDA8 3V3 Power 191 STATMUXOUT 3 PO22F tri PIC Status output configuration input 192 STATMUXOUT 4 PO22F tri PIC Status output configuration inp...

Page 31: ...explanation of what the signal does Type The type of signal The sections below define the pin out of the SpaceWire router Its interfaces are split into several types separated by headings for clarity 5 1 Global signals clock and reset 5 2 SpaceWire interface signals 5 3 External port signals 5 4 Time code interface signals 5 5 Configuration signals 5 6 Reset configuration signals 5 7 Power and Gro...

Page 32: ... CMOS3V3 Internal pull down 10 9 6 FEEDBDIV 2 FEEDBDIV 1 FEEDBDIV 0 In Set the output clock rate of the internal PLL as follows 000 Æ 100MHz 001 Æ 120MHz 010 Æ 140MHz 011 Æ 160MHz 100 Æ 180MHz 101 Æ 200MHz 110 Æ 200MHz 111 Æ 200MHz See section 8 1 6 for setting the transmit rate CMOS3V3 Internal pull down See section 10 1 for timing details WARNING Simultaneous data strobe transitions can occur du...

Page 33: ...a part of Data Strobe SpaceWire port 7 LVDS P Side LVDS N Side 97 96 DOUTPlus 8 DOUTMinus 8 Out Differential output pair data part of Data Strobe SpaceWire port 8 LVDS P Side LVDS N Side 22 21 SOUTPlus 1 SOUTMinus 1 Out Differential output pair strobe part of Data Strobe SpaceWire port 1 LVDS P Side LVDS N Side 32 31 SOUTPlus 2 SOUTMinus 2 Out Differential output pair strobe part of Data Strobe Sp...

Page 34: ...DS N Side 88 89 DINPlus 8 DINMinus 8 In Differential input pair data part of Data Strobe SpaceWire port 8 LVDS P Side LVDS N Side 19 20 SINPlus 1 SINMinus 1 In Differential input pair strobe part of Data Strobe SpaceWire port 1 LVDS P Side LVDS N Side 27 28 SINPlus 2 SINMinus 2 In Differential input pair strobe part of Data Strobe SpaceWire port 2 LVDS P Side LVDS N Side 37 38 SINPlus 3 SINMinus 3...

Page 35: ...ing a small positive voltage across the bias resistor and forcing the output of the LVDS receiver to logic 1 Now any noise current smaller than this bias current will not cause the receiver to transition The bias current can be supplied by a pair of resistors connected to the power and ground rails as illustrated in Figure 5 1 R1 RT R2 In In Ib Disconnected Inputs 3V3 Figure 5 1 LVDS Receiver Fail...

Page 36: ... of R2 to the total resistance RB The line common mode voltage Vcm should be 1 25 V so the ratio of R2 to RB is R2 RB 1 25 V 3 3 V 0 379 4 Calculate the value of R2 and round down to a standard value E g R2 0 379 x 33 kΩ 12 5 kΩ so the nearest standard value is 12 kΩ E24 series 5 Now recalculate the value of RB to give the required line common mode voltage E g RB 12kΩ 0 379 V 31 6 kΩ 6 Calculate t...

Page 37: ...signals is shown in Figure 6 1 External port write timing specification and Figure 6 2 External port read timing specification Table 5 3 External Port Interface Signals PinNo Signal Dir Description Type 112 111 110 107 104 103 102 101 100 EXT9_OUT_DATA 8 EXT9_OUT_DATA 7 EXT9_OUT_DATA 6 EXT9_OUT_DATA 5 EXT9_OUT_DATA 4 EXT9_OUT_DATA 3 EXT9_OUT_DATA 2 EXT9_OUT_DATA 1 EXT9_OUT_DATA 0 Out Output data f...

Page 38: ... 137 136 133 132 131 130 129 128 EXT10_OUT_DATA 8 EXT10_OUT_DATA 7 EXT10_OUT_DATA 6 EXT10_OUT_DATA 5 EXT10_OUT_DATA 4 EXT10_OUT_DATA 3 EXT10_OUT_DATA 2 EXT10_OUT_DATA 1 EXT10_OUT_DATA 0 Out Output data from external port number two FIFO Bit eight determines the type data eop or eep The encodings are defined as 8 7 0 Bits 0 dddddddd Data byte 1 XXXXXXX0 EOP 1 XXXXXXX1 EEP Bit 7 is the most signific...

Page 39: ...al FIFO port 10 is not being used CMOS3V3 See section 6 1 for information on the operation of the external ports and section 10 3 for timing details 5 4 TIME CODE SIGNALS The time code interface signals are listed in Table 5 4 The timing of this interface is shown in Figure 6 3 and Figure 6 4 Table 5 4 Time Code Signals PinNo Signal Dir Description Type 158 EXT_TICK_IN In The rising edge of the EX...

Page 40: ...l time code register and propagated by the router If SEL_EXT_TIME is low on the rising edge of EXT_TICK_IN the value to be sent in the time code will be taken from the internal time code counter in the router The two control bits bits 7 6 of the time code will come from bits 7 6 of the EXT_TIME_IN 7 0 input If the time code port is not being used this input should be pulled down e g 4k7 Ω CMOS3V3 ...

Page 41: ...T_MUX_OUT as defined in Table 6 1 These inputs should be driven or pulled up or down e g 4k7 Ω depending on what information is required from the status outputs CMOS3V3 195 194 193 192 191 188 187 186 STAT_MUX_OUT 7 STAT_MUX_OUT 6 STAT_MUX_OUT 5 STAT_MUX_OUT 4 STAT_MUX_OUT 3 STAT_MUX_OUT 2 STAT_MUX_OUT 1 STAT_MUX_OUT 0 inout Multi function pin Power on Configuration After reset the STAT_MUX_OUT pi...

Page 42: ... following RST being de asserted The status output STAT_MUX_OUT is driven on the fourth CLK cycle after RST is de asserted See section 6 3 for information on the operation of the status power on configuration interface and section 10 5 for timing details 5 6 RESET CONFIGURATION SIGNALS The Reset Configuration signals are listed in Table 5 6 These signals are input on STAT_MUX_OUT after reset to in...

Page 43: ...ATE affects all SpaceWire ports in the router Note The data rate is dependent on FEEDBDIV at reset CMOS3V3 STAT_MUX_OUT 3 maps to POR_ADDR_SELF_N In If asserted low after reset allows a router port to address itself and therefore cause an input packet to be returned through the same input port This mode may only be suitable for debug and test operations This signal is active low CMOS3V3 STAT_MUX_O...

Page 44: ...AT_MUX_OUT 7 maps to POR_DSBLE_ON_SILENCE_N In Power on reset signal which determines if the output ports are disabled when no activity is detected on an output port for the current timeout period When asserted low an output port is disabled when it has not sent any information for longer than the current timeout period This signal is active low CMOS3V3 WARNING In most onboard applications it is r...

Page 45: ... connection for the device GND VCOBias PLL VCO Bias analogue VSSPLL PLL Supply 3V3 VDDPLL PLL Supply GND LoopFilter PLL Loop Filter analogue LVDSref LVDS Buffer reference analogue 5 7 2 Decoupling The power pins should be decoupled to the ground plane One 100 nF decoupling capacitor should be used for each power pin 5 7 3 LVDS Reference An external resistor is required to provide a reference for t...

Page 46: ...bias resistor depends on the required VCO frequency range which is determined by the PLL feedback divider NF in Figure 5 3 The VCO bias resistor values to use are Rvco 4 7 kΩ for 100 150MHz FEEDBDIV 0b000 0b001 or 0b010 Rvco 1 8 kΩ for 150MHz 200MHz FEEDBDIV 0b011 0b100 0b101 or 0b110 or 0b111 See section 5 1 for information about the FEEDBDIV inputs A dedicated decoupling capacitors 100 nF and 1µ...

Page 47: ... physical signal is logic 0 low when the external input FIFO is full 6 1 EXTERNAL PORT INTERFACE OPERATION In this section the external port interface operation is described CLK 1 2 3 4 5 6 7 8 9 10 11 12 EXT_IN_FULL_Nx EXT_IN_DATAx EXT_IN_WRITE_Nx DATA EOP DATA DATA Figure 6 1 External port write timing specification The operation of the External port during write operations starts with the EXT_I...

Page 48: ...f there is no more data available in the FIFO then the EXT_OUT_EMPTY_N is de asserted once the data has been read If the FIFO contains more data to transfer then the EXT_OUT_EMPTY_N remains asserted the new data is placed on the EXT_OUT_DATA bus and the external system can read it as soon as it is ready The read access is ignored if there is no data available EXT_OUT_EMPTY_N is active 6 2 TIME COD...

Page 49: ...ating time codes see SpaceWire standard AD1 EXT_TICK_OUT EXT_TIME_OUT Figure 6 4 Time Code Output Interface When a valid time code is received by the router the value of this time code flags plus time value will be placed on the EXT_TIME_OUT outputs and the EXT_TICK_OUT signal will be set to zero The EXT_TICK_OUT signal is set to one a short time later once the EXT_TIME_OUT outputs have stabilised...

Page 50: ...ermination Protocol byte error Invalid address data error 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 1 8 SpaceWire Ports 1 8 respectively Packet Address Error Output Port Timeout Disconnect Error Parity Error Escape Error State A State B State C 1 2 3 4 5 8 9 10 0 1 2 3 4 5 6 7 9 10 External Ports 0 1 respectively Error Active Packet Address Error Output Port Timeout Input Buffer Empty Input Buffer Full Outp...

Page 51: ...ose Least Significant 8 bits 7 0 7 0 6 4 RESET CONFIGURATION INTERFACE OPERATION CLK RSTN POR_SIGNA LS POR_SS 1 2 3 4 5 6 7 8 9 Figure 6 7 Reset configuration interface timing specification The POR configuration signals POR_SIGNALS listed above are loaded into the appropriate internal configuration registers of the router on the first rising edge of the system clock CLK after RSTN is de asserted T...

Page 52: ...internal SpaceWire router routing table can be set up to assign logical addresses to the physical ports except the configuration port port 0 which can only be accessed by path addressing The physical port addresses for the SpaceWire router and the expected packet type is defined in the table below The packet types can be viewed in section 0 Table 7 1 Packet Address Mapping Packet Address Expected ...

Page 53: ...e link port 2 3 HIGH SpaceWire link port 3 4 HIGH SpaceWire link port 4 5 HIGH SpaceWire link port 5 6 HIGH SpaceWire link port 6 7 HIGH SpaceWire link port 7 8 HIGH SpaceWire link port 8 9 HIGH External FIFO port 1 10 HIGH External FIFO port 2 11 31 N A Invalid addresses 32 255 Dependent on routing table Default LOW May be configured HIGH see section 9 3 Logical addresses 7 3 PACKET HEADER DELETI...

Page 54: ...e changed by configuration Header deletion for logical addresses can be enabled or disabled via a configuration register see section 9 3 7 4 INVALID ADDRESSES Packets which have invalid addresses are discarded by the routing control logic Path addresses which are in the range 11 31 logical addresses which are set as invalid in the routing table and empty packets packets with no address or cargo in...

Page 55: ...ss is zero Command packets perform write and read operations to registers in the SpaceWire router Command packets accepted by the SpaceWire router are in the form shown in Figure 7 2 Configuration read packets are in the form ADDRESS 0 COMMAND EOP Figure 7 2 Command Packet Format The SpaceWire router supports the Remote Memory Access Protocol RMAP AD2 for configuration of the internal router contr...

Page 56: ...s Yes 1000 Write single address no verify no acknowledge No 1001 Write incrementing address no verify no acknowledge No 1010 Write single address no verify send acknowledge No 1011 Write incrementing address no verify send acknowledge No 1100 Write single address verify data no acknowledge No 1101 Write incrementing address verify data no acknowledge No 1110 Write single address verify data send a...

Page 57: ...he first byte received by the SpaceWire router configuration logic is the port address followed by the destination logical address Fields which are depicted in bold text are expected values Fields which are shaded are optional Read Address MS 00h Read Address 00h Read Address Read Address LS Data Length MS 00h Data Length 00h Data Length LS 04h Header CRC Config Port Address 00h EOP Last Byte Rece...

Page 58: ... defined in section 7 6 9 1 Destination Key The destination key identifier must match the contents of the destination key register see section 9 5 10 The default power on destination key is 20h 1 Source Path Address The source path address field is used to add source path addresses to the head of the reply packet The expected number of source path addresses is specified in the command byte See sec...

Page 59: ... Source Path Address Source Logical Address Protocol Identifier 01h Packet Type Command Source Path Addr Len Status Destination Logical Address FEh Transaction Identifier MS Transaction Identifier LS Reserved 0 Data Length MS 00h Data Length 00h Data Length LS 04h Header CRC Data Word 0 MSB Data Data Data Word 0 LSB Source Path Address Source Path Address Data CRC EOP First byte transmitted Last b...

Page 60: ...dentifier The transaction identifier identifies the command packet and reply packet with a unique number The transaction identifier in the reply packet is copied from the command packet and returned in this field so that the command and the corresponding reply have the same transaction identifier value 2 Data Length The data length field is set to 4 bytes as this is a single read command 3 Header ...

Page 61: ...ess 32 bit aligned Accepted Logical Addresses 0xFE Accepted destination keys 0x20 at power on Accepted address ranges 0x00 0000 0000 0x00 0000 0109 Incrementing address Incrementing address only The RMAP read incrementing address command is supported in the SpaceWire router The read incrementing address is used to read a continuous block of registers from the SpaceWire router e g the complete grou...

Page 62: ...ead Address 00h 0 0 1 1 1 0 Bits in Packet Type Command Source Path Address Length Byte MSB Packet Type Command Source Path Address Length Source Path Address Length LSB Source Path Address Length First Byte Received Figure 7 5 Read Incrementing Address Command Format Table 7 9 Read Incrementing Address Command Packet Fields Field Description Bytes Config Port Address The configuration port addres...

Page 63: ...of FEh 1 Transaction Identifier The transaction identifier identifies the command packet and reply packet with a unique number 2 Extended Read Address The extended read address is not used in the SpaceWire router and shall always be set to zero 1 Read Address The read address identifies the start address for the read incrementing command The valid starting read addresses are defined in section 9 4...

Page 64: ...ifier LS Reserved 0 Data Length MS 00h Data Length Data Length LS Header CRC Data Word 0 MSB Data Data Data Word 0 LSB Source Path Address Source Path Address Data Word 1 MSB Data Data Data Word 1 LSB Data CRC EOP First byte transmitted Last byte transmitted 0 0 0 1 1 0 Bits in Packet Type Command Source Address Path Length Byte MSB Packet Type Command Source Path Address Length Source Path Addres...

Page 65: ...rned in this field so that the command and the corresponding reply have the same transaction identifier value 2 Data Length The data length field is the number of bytes read from the router as specified in the data length field of the command packet 3 Header CRC The header CRC used to detect errors in the header part of the command packet See section 7 6 7 for CRC generation 1 Data The data read f...

Page 66: ...uter configuration logic is the port address followed by the destination logical address Fields which are depicted in bold text are expected values Fields which are shaded are optional Destination Logical Address FEh Protocol Identifier 01h Packet Type Command Source Path Addr Len Destination Key Source Path Address Source Path Address Source Path Address Source Path Address Source Logical Address...

Page 67: ...quired as defined in section 7 6 9 1 Destination Key The destination key identifier must match the contents of the destination key register see section 9 5 10 1 Source Path Address The source path address field is used to add source path addresses to the head of the reply packet The expected number of source path addresses is specified in the command byte See section 7 6 9 for source path address ...

Page 68: ...register dependent on the contents of the register Register Data the command data Command Data and the command mask value Mask as follows Register Value Mask AND Command Data OR NOT Mask AND Register Data An example is shown below the highlighted bits are set or reset by the command 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 23 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 15 0 7 Command Data 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 69: ...SB Source Path Address Source Path Address Data CRC EOP First byte transmitted Last byte transmitted 0 1 0 1 1 0 Bits in Packet Type Command Source Path Address Length Byte MSB Packet Type Command Source Path Address Length Source Path Address Length LSB Source Path Address Length Figure 7 9 Read Modify Write Reply Packet Format Table 7 13 Read Modify Write Reply Packet Fields Field Description By...

Page 70: ...The header CRC used to detect errors in the header part of the command packet See section 7 6 7 for CRC generation 1 Data The data read from the SpaceWire router registers before the modify operation is performed 4 Data CRC The data CRC used to detect errors in the data part of the reply packet See section 7 6 7 for CRC generation 1 7 6 5 Write Command The write command characteristics of the Spac...

Page 71: ...ction Identifier LS Extended Write Address 00h Write Address MS 00h Write Address 00h Write Address Write Address LS Data Length MS 00h Data Length 00h Data Length LS 04h Header CRC Data MSB Data Data Data LSB Config Port Address 00h Data CRC EOP 1 1 1 0 1 0 Source Path Address Length Source Path Address Length Bits in Packet Type Command Source Path Address Length Byte MSB LSB Packet Type Command...

Page 72: ...e Logical Address The source logical address should be set to the logical address of the node which sent the command 1 Transaction Identifier The transaction identifier identifies the command packet and reply packet with a unique number 2 Extended Write Address The extended write address is not used in the SpaceWire router and is always expected to be zero 1 Write Address The write address identif...

Page 73: ... transmitted 1 1 0 0 1 0 Bits in Packet Type Command Source Path Address Length Byte MSB Packet Type Command Source Path Address Length Source Path Address Length LSB Source Path Address Length Figure 7 11 Write Single Address Reply Packet Table 7 16 Write Single Address Reply Packet Fields Field Description Bytes Source Path Address Optional source path addresses specified in the command packet I...

Page 74: ...rt status register Table 7 17 Configuration Port Errors Summary Register Bits Description Reply Packet Returned As Returned RMAP Status Code Invalid Header CRC The header CRC was invalid therefore the header is corrupted No No Reply Packet Unsupported Protocol Error The protocol byte is not the RMAP protocol identifier No No Reply Packet Source Logical Address Error The source logical address is i...

Page 75: ...e data length field is invalid when performing a verified write command The valid length is 4 bytes of data Yes Verify Buffer Overrun 9 Command not implemented A command code was received which is not supported by the SpaceWire router Supported command codes are listed in F1 18 Yes RMAP Command not implemented or not authorised 10 Invalid Data Length The data length field is invalid A data length ...

Page 76: ... logical address is expected to be the default 254 value Yes Invalid Destination Logical Address 12 7 6 7 Command Packet Cyclic Redundancy Check The header and data part of an RMAP packet are protected from errors by the use of an 8 bit CRC code The header and data CRC is formed using the CRC 8 code used in ATM Asynchronous Transfer Mechanism CRC 8 has the polynomial 1 1 2 8 X X X with a starting ...

Page 77: ...n the packet any following zeros shall be treated as an error A source path address sequence is reported see section 7 6 6 The table below gives some examples of how to set the source path address length and packet address fields for the required path addresses Table 7 18 Source Path Address Reference Table Source Path Address Length RMAP Source Path Address fields FirstÆLast Transmitted Reply Pat...

Page 78: ...gical address byte which in the router is expected to be the default 254 value The format is shown in Figure 7 14 Path Address 0 Dest Logical Address 254 Protocol ID 1 RMAP Header Figure 7 14 Normal Configuration Packet Header Structure To allow source nodes which have a 16 24 or 32 bit access port then the configuration port accepts up to three null bytes at the start of the packet The null bytes...

Page 79: ...e link data rate divider can also be set in the link control register The following paragraphs define each of the link control functions 8 1 1 Default operating mode The default operating mode is Auto Start This is the mode setting for each link after power on or reset 8 1 2 Auto Start In auto start mode the SpaceWire port will remain inactive until a connection attempt is made by the SpaceWire de...

Page 80: ...ed control bits in the SpaceWire port control register see section 9 4 3 and on the Enable Start on Request bit in the router control register see section 9 5 3 When Auto start is enabled and the deactivate bit is set then the data and strobe LVDS drivers are deactivated until the interface receives a connection attempt by an external SpaceWire device The drivers are then enabled until the externa...

Page 81: ...DOUT deactivate driver disable is performed one CLK cycle before the SOUT deactivate avoiding any simultaneous transitions on Data or Strobe When the LVDS drivers are deactivated the equivalent circuit of these outputs is a shown in Figure 8 2 3 3 V Out Out 2850 Ω 2850 Ω 1725 Ω 1725 Ω Vdd Vss Deactivated NMOS Transistors off Figure 8 2 Deactivated LDVS driver output When external bias resistors ar...

Page 82: ...ed up to 3 3V and have an impedance of the order of 1 kohm Since they are differential outputs and are both are at the same voltage no current will flow If however external noise bias resistors are being used then a small current around 200 µA 0 7 mW power can flow This is substantially less than the normal operating current of LVDS outputs and hence saves power 8 1 6 Setting the SpaceWire port tr...

Page 83: ... 50 0 33 33 25 0 20 0 16 67 14 29 12 5 11 11 10 0 9 09 10 000 9 11 5 1 9 100 0 50 0 33 33 25 0 20 0 16 67 14 29 12 5 11 11 10 0 9 09 10 000 9 11 4 1 8 90 0 45 0 30 0 22 5 18 0 15 0 12 86 11 25 10 0 9 0 8 18 10 000 1 1 3 1 7 80 0 40 0 26 67 20 0 16 0 13 33 11 43 10 0 8 89 8 0 7 27 10 000 7 9 2 1 6 70 0 35 0 23 33 17 5 14 0 11 67 10 0 8 75 7 78 7 0 6 36 10 000 1 1 1 1 5 60 0 30 0 20 0 15 0 12 0 10 0...

Page 84: ...a bit period This can reduce skew tolerance and hence the maximum operating speed of the SpaceWire ports Taking a limit of 10 of the bit period allows the use of 10Mbit s clocks with a duty cycle of 9 11 as the worst case The corresponding setting for the TX10MbitDIV field in the transmit clock register see section 9 5 9 is given in the third column Only the rows with valid Initialisation data rat...

Page 85: ...he link If a connection can be made then the packet is forwarded on towards its destination This is illustrated in Figure 8 4 This mode allows the SpaceWire ports to be started automatically when there is data to send This can be used together with output deactivate to save power R1 R2 1 2 1 2 Auto Start default mode and Start on Request enabled in both routers R1 R2 1 2 1 2 2 Packet with address ...

Page 86: ...isable a SpaceWire port when the SpaceWire router is the source of the data transfer If an external device starts the SpaceWire link or sends packet data to the router through the link then the link will not be disabled 8 3 CONTROL LOGIC AND ROUTING This section describes the operation of the SpaceWire routing logic and how packets are handled for different modes of operation of the router The fol...

Page 87: ... can cause substantial delays in transferring information The following sub sections illustrate the various scenarios where arbitration is necessary 8 3 2 1 Arbitration of packets with matching priority 1 In the Figure 8 6 an example of arbitrating between packets with the same priority is illustrated Only router ports 1 5 are shown for clarity At stage one input ports 1 and 3 have packets to be r...

Page 88: ...le the packet from input port 1 is being transferred to output port 5 another packet arrives at input port 2 to be routed to output port 5 At stage three the packet from input port 1 has been forwarded and the packet from input port 2 is selected by the router to be routed through output port 5 Input port two is selected before input port 3 as it is the next input port to be considered by the rout...

Page 89: ...t port 1 has a packet waiting with logical address 80 which is high priority input port 1 will be selected first and the packet with logical address 80 transferred to output port 5 At stage three the high priority packet with logical address from input port 1 has been transferred and the remaining low priority packet from input port 3 is selected by the router to be transferred to output port 5 R1...

Page 90: ...5 In the meantime a packet with low priority logical address 52 arrives at input port 4 At stage number four the high priority packet from input port 4 has been forwarded and the routing control logic arbitrates again for access to output port 5 There are no high priority packets waiting to use output port 5 so the low priority packets that are waiting are considered The previous low priority pack...

Page 91: ...rom port 1 completes HIGH priority packet from port 4 is selected Port number 3 waits Packet arrives on port 1 R1 2 5 1 3 4 Packet from port 4 completes Previous low priotity packet which accessed port 5 1 Therefore port 3 is selected Packet on port 1 waits 1 2 3 4 Addresses 80 HIGH Priority 52 LOW Priority 80 52 52 R1 2 5 1 3 4 Packet from port 3 completes Packet waiting on port 1 is selected 5 R...

Page 92: ... Arbitration is performed on group adaptive routing packets as defined in section 8 3 2 The following sub section consider various situations that can occur during group adaptive routing 8 3 3 1 Normal Group adaptive routing In normal group adaptive routing the lowest numerical output port in the group that is ready to use is used to transfer the packet This is illustrated in Figure 8 10 R1 1 2 3 ...

Page 93: ... it is running and not being used to route another packet R1 1 2 3 4 5 6 76 Group adaptive routing packet with address 76 arrives at port 1 Ports 4 and 5 are not ready to accept packet data Address 76 Routing table entry Header Deletion disabled Port 4 Port 5 Port 6 1 2 R1 1 2 3 4 5 6 76 Routing logic assigns ports 6 to packet at port 1 X X X X Figure 8 12 Group adaptive routing when ports not rea...

Page 94: ...rrived on are not affected by the value of the Enable Self Addressing bit Figure 8 13 shows the Enable Self Addressing mode when enabled and when disabled R1 1 2 3 4 5 6 1 R1 1 2 3 4 5 6 1 2 Packet arrives at port 1 with address 1 Address self mode is enabled Packet is routed to port 1 and packet data returns on link one R1 1 2 3 4 5 6 1 R1 1 2 3 4 5 6 1 2 Packet arrives at port 1 with address 1 A...

Page 95: ... first data character of a packet In this way the time to transfer a complete packet is not checked but instead the watchdog timers check if a packet has blocked i e no data transfers A blocked packet is spilt by terminating the packet at the router output port with an EEP and spilling the remainder of the packet to be transmitted up to and including the EOP at the router input port If the router ...

Page 96: ...clarity a A packet arrives at port 3 of routing switch R1 destined for port 4 and then port 5 of R2 as shown by the path address 4 5 at the head of the packet R1 1 2 3 4 5 6 a 4 5 R2 1 4 2 3 5 6 Figure 8 14 Destination Node Blocked a b The packet is routed towards its destination but during packet transfer the destination stalls and does not accept any more data The network path is blocked and the...

Page 97: ...e packet is routed towards its destination but during packet transfer the destination stalls and does not accept further data The network path is blocked and the packet waiting at R1 port 2 is also blocked R1 1 2 3 4 5 6 b R2 1 4 2 3 5 6 4 4 Figure 8 18 Destination Node Blocked Watchdog Mode b c At routing switches R1 and R2 the watchdog timers detect the packet has blocked for the specified timeo...

Page 98: ...data part way through sending a packet A router will see this situation as an input port which has stalled no longer sending data part way through sending a packet although the SpaceWire link is still running This situation can occur due to an error in the network or in the node that was providing data In blocking allowed mode the network path will be blocked until the source node supplies the end...

Page 99: ...and the packet waiting at routing switch R1 port 2 cannot be routed R1 1 2 3 4 5 6 c R2 1 4 2 3 5 6 4 4 Figure 8 23 Source Node Stalled c d After an undetermined time the source node supplies the remaining data and end of packet and the packet waiting at R1 2 can be routed R1 1 2 3 4 5 6 d R2 1 4 2 3 5 6 Figure 8 24 Source Node Stalled d Watchdog Timer Mode What happens when a source stalls and Wa...

Page 100: ...alled Watchdog Mode b c The packet is blocked and the packet waiting at routing switch R1 port 2 cannot be routed The watchdog timers in routing switches R1 and R2 detect the packet has become blocked and spills data from the input port and appends an error end of packet to the output port This causes the network path from routing switch R1 port 4 to routing switch R2 port 1 to be cleared and the ...

Page 101: ...uter and the output port that it is to be router to is running but not currently sending a packet then the newly arrived packet will be routed immediately Output port running and busy If a packet arrives at an input port on the SpW 10X router and the output port that it is to be router to is running and currently sending a packet the newly arrived packet will wait indefinitely for the output port ...

Page 102: ...e spilled in a SpaceWire network without the destination receiving any notification of this Packets with errors e g parity error can arrive at a destination terminated by an EEP In a very special case it is also possible to receive an error free packet terminated by an EEP It is important that the destination node is able to handle these cases ...

Page 103: ...ter description There are 263 registers in the configuration port addresses Registers that are shorter than 32 bits or that have unused fields will return zero in all the unused bit positions when read The unused bit positions are ignored during writing but should in any case be set to zero 9 1 INTERNAL MEMORY MAP The memory map for the SpaceWire Router is shown in Figure 9 1 GROUP ADAPTIVE ROUTIN...

Page 104: ...Register within Configuration Port Register Name Description Address Group Adaptive Routing Table Registers Allows the setting of group adaptive routing logical addresses by assigning the output ports which should be accessed when a packet is received with logical address 32 255 0x20 0xFF Port Control Status Registers Controls the Configuration SpaceWire and External Ports Provides the status of t...

Page 105: ...Manufacturer and Chip ID register 262 0x0000 0106 General Purpose register 263 0x0000 0107 Time Code Enable register 264 0x0000 0108 Clock Control register 265 0x0000 0109 Destination Key Register 9 3 GROUP ADAPTIVE ROUTING TABLE REGISTERS The Group Adaptive Routing GAR table is accessed through configuration memory addresses 32 255 0x0000 0020 0x0000 00FF The fields in the GAR registers are illus...

Page 106: ...n a bit is set in the REQUEST field packets may be routed to the corresponding output ports The port number corresponds to the bit position in the GAR register For example if configuration memory address 39 has bit 2 set then a packet with logical address 39 may be routed out of port 2 If bits 2 and 4 are both set then the packet may be routed out of either port 2 or 4 Port 0 the configuration por...

Page 107: ...its 10 1 are set to zero then the INVALID_ADDR bit will be set and all other bits will be set to zero Note The configuration port port 0 is not accessible through logical addresses R W 28 11 NOT USED 29 DEL_HEAD Undefined after power on Unaltered by reset Delete header when set the leading header byte of the input packet will be removed before it is transferred to the output port R W 30 PRIORITY U...

Page 108: ... 4 PORT CONTROL STATUS REGISTERS The port control status registers address range is 0 31 0x0000 0000 0x0000 001F The port control status registers provide the means to configure and control the ports of the router and for reading the status of each port There is a port control status register for each SpaceWire port each External port and for the configuration port The address in configuration mem...

Page 109: ...ort This is the reset condition R 31 29 Port Type All bits set to zero Indicates the port type Possible port types are listed below 000 Configuration port 001 SpaceWire port 010 External port R 9 4 2 Configuration port control status register fields The configuration port control status fields specific to the configuration port are described in Table 9 5 Any errors occurring in the configuration p...

Page 110: ...ted by the SpaceWire Router R 6 Invalid Data Length 0 The invalid data length bit is set when a data length error is detected R 7 Invalid RMW Data Length 0 The read modify write command data length is invalid When a read modify write is performed the expected data length is 8 R 8 Invalid Destination Logical Address 0 The invalid destination logical address bit is set when the destination logical a...

Page 111: ... The unsupported protocol error bit is set when a command packet is received with a protocol identifier which is not the RMAP protocol identifier of 01h R 16 Source logical address error 0 The source logical address error bit is set when an invalid source logical address is received R 17 Not used 0 This bit in the register is not used R 18 Cargo too large 0 The RMAP command packet is too large R 1...

Page 112: ...control status fields specific to SpaceWire ports are shown in Figure 9 3 and Table 9 6 Error Status 0 7 11 8 15 12 16 22 27 24 31 28 Interface State Interface Control Transmit Rate Arbiter Connection Port Type Not Used 23 Figure 9 3 SpaceWire Port Control Status Register Fields Note Error status bits are cleared by writing to the Error Active register see section 9 5 4 ...

Page 113: ... link R 4 Parity error 0 The parity error bit is set when a parity error occurs on the SpaceWire link R 5 Escape error 0 The escape error bit is set when an escape error occurs on the SpaceWire link R 6 Credit error 0 The credit error bit is set when a credit error occurs on the SpaceWire link R 7 Character sequence error 0 The character sequence error bit is set when a character sequence error oc...

Page 114: ...15 Deactivate 0 When set the DOUT and SOUT serial SpaceWire signals will be deactivated dependent on the state of the SpaceWire link interface The DOUT and SOUT deactivate output state mappings are listed below ErrorReset Æ Deactivate ErrorWait Æ Deactivate Ready Æ Deactivate Started Æ Enabled Connecting Æ Enabled Run Æ Enabled Note DOUT is deactivated one system clock cycle before SOUT to ensure ...

Page 115: ...cked for a period of time R 3 Input Buffer Empty 0 The external port input buffer is empty Note The input buffer writes data to the SpaceWire router R 4 Input Buffer Full 0 The external port input buffer is full R 5 Output Buffer Empty 0 The external output port buffer is empty Note The output buffer writes data to the external device connected to the external port R 6 Output Buffer Full 0 The ext...

Page 116: ...n Port All bits set to zero Indicates the input port number which accessed this network discovery register R 31 8 Ports in Run state All bits set to zero Indicates the SpaceWire ports which are in the run state Bit 8 corresponds to SpaceWire port 1 The external ports are the highest numbered port and the corresponding register bits are set to one In this way a network manager can determine the num...

Page 117: ...unctions which can be controlled are Request an output port to initiate start up when an input packet addresses that output port but it is not ready to receive data Disconnect a SpaceWire port when no activity is detected on the port for the timeout period duration Enable output port timeouts which request the output port to flush when a packet becomes blocked for a timeout period Enable the a rou...

Page 118: ...µs When 1 timeout period is 1 3 ms Selects the blockage timeout period Values as below 000 60 80 µs N 2 001 1 3 ms N 6 010 10 ms N 9 011 82 ms N 12 100 1 3 s N 16 101 1 3 s N 16 110 1 3 s N 16 111 1 3 s N 16 The actual value of the timeout period is given by 200 x 2 N x TCLK 200 x TCLK where TCLK is the period of the 10 MHz clock signal R W 4 Enable disable on silence Set by the input signal POR_D...

Page 119: ...Note if the output port link disable bit is set then the link will not start R W 6 Enable Self Addressing Set by the input signal POR_ADDR_SELF_N When set input ports are permitted to address themselves If this bit is not set and a packet is to be routed through the same port then an address error is reported and the packet is discarded When this bit is not set and a group adaptive routing packet ...

Page 120: ...Error active Register The error active register address is 259 0x0000 0103 The error active register indicates the Error Active bit of the each of the port control status registers By reading from this register a network manager can determine which ports currently have errors This register is also used to clear the error bits of the port control status registers To do this a write command is sent ...

Page 121: ...t is asserted A write to this register with one or more of these bits set will clear all the error flags in the corresponding SpaceWire and External port control status registers When writing to this register with all bits set all error flags in all port control status registers are cleared Note only bits 10 1 are used in the SpW 10X router R W 31 Not used All bits set to zero Not used because the...

Page 122: ...hip identity and version number The fields of the device manufacturer and chip ID register are shown in Figure 9 8 and described in Table 9 13 Version number 31 Chip ID code Manufacturer Code 24 23 16 15 8 7 0 Not used Figure 9 8 Device Manufacturer and Chip ID Register Fields Table 9 13 Device Manufacturer and Chip ID Register Fields Bits Name Reset Value Description Read Write 7 0 Version Number...

Page 123: ...ter Bits 1 to 8 of the time code enable register are used to enable time code distribution through SpaceWire ports 1 to 8 respectively If one of these bits is set to 1 then the corresponding SpaceWire port is enabled for time code distribution and will send out a time code when one is received by the router For example if bit 1 in the enable register is set to 1 time codes are passed to SpaceWire ...

Page 124: ...0 then valid time codes are distributed When the time code control flags are not 00 then the time code is discarded and the internal time code register is not updated R W 31 13 Not used All bits set to zero R 9 5 9 Transmit Clock Control Register The transmit clock control register address is 264 0x0000 0108 The transmit clock control register is shown in Figure 9 10 Bits 1 to 0 are used to determ...

Page 125: ...t clock turned off then it will not be possible to configure the router using that port Unless there is another connection with an active clock and which is not disabled that can be used to perform configuration the router will have to be reset before it can be configured again TXDIV 0 15 8 Not used 1 2 7 Enable clock 16 20 Tx10MbitDIV 21 32 Not used Figure 9 10 Transmit clock control register ...

Page 126: ...cy will be 50MHz and the transmit data rate will be 100Mbit s R W 7 2 Not used All bits set to zero R 15 8 Enable clock All bits set to 1 Enable the transmit clock trees Setting a bit to zero disables the transmit clock for the corresponding SpaceWire port i e clearing bit 8 causes the transmit clock for SpaceWire port 1to be stopped R W 20 16 Tx10MbitDIV Dependent on FEEDBDIV at reset FEEDBDIV 00...

Page 127: ...et to zero 9 5 11 Unused Registers and Register Bits If an unused register address is referenced in a configuration command then the command will not be acted upon and a NACK will be sent in the reply to the command All unused bits in valid configuration registers will return 0 when read 9 5 12 Empty packets An empty packet received at the configuration port is discarded by the configuration port ...

Page 128: ... TCH 35 2 TBC ns max Clock minimum pulse width TACLK 5 ns min Clock input jitter TCJITTER 2 ns max PLL lock time after reset TPLLLOCK 20 µs max Reset minimum pulse width TARST 5 ns min Reset end till operational TRST2OP 20 ns max 1 The PLL max frequency is 200 MHz TBD MHz 2 The PLL min frequency is 100 MHz TBD MHz 10 2 SERIAL SIGNALS TIMING PARAMETERS The data strobe minimum consecutive edge separ...

Page 129: ...INS2 7 5 ns min Data Strobe output skew jitter incl LVDS driver TDSOSKEWJIT 1 2 ns max 10 3 EXTERNAL PORT TIMING PARAMETERS The external port input timing parameters can be viewed below CLK EXT_IN_WRITE_N EXT_IN_DATA EXT_IN_FULL_N TEXTFFCKO TEXTODATSU TEXTODATHLD TEXTWRSU TEXTWRHLD Figure 10 2 External port input FIFO timing parameters The external port input timing parameters can be viewed below ...

Page 130: ...put TEXTFFCKO 5 ns min CLK rising edge to full flag output TEXTFFCKO 18 ns max Read enable setup time to CLK rising edge TEXTRDSU 5 ns min Read enable hold time after CLK rising edge TEXTRDHLD 5 ns min CLK rising edge to read data output TEXTODATCKO 5 ns min CLK rising edge to read data output TEXTODATCKO 18 ns max CLK rising edge to empty flag output TEXTEFCKO 5 ns min CLK rising edge to empty fl...

Page 131: ...on Symbol Value Units Tick in and time reset low time TTCLKIL 1 CLK period 5 ns min Tick in and time reset high time TTCLKIH 1 CLK period 5 ns min Select external time and Time code in set up time TTCLKISU 5 ns max Select external time and Time code in hold time TTCLKIHLD 5 ns max Tick out low time TTCLKOL 3 CLK periods 5 ns Min to max Tick out high time TTCLKOH 4 CLK periods 5 ns min Time code ou...

Page 132: ...re Router User Manual Date 11th July 2008 Preliminary 132 Table 10 5 Status Multiplexer timing parameters Description Symbol Value Units Status address change to status output change TSTMUX 3 to 20 ns CLK rising edge to status output TCLKSTMUX 5 to 25 ns ...

Page 133: ...eriods System Clock Period TSYSPERIOD 33 333 ns Clock Frequency 30 MHz Transmit Clock Period TTXPERIOD Transmit bit rate period 2 Where Transmit bit rate period is the output bit rate selected by the user configuration Receive Clock Period TRXPERIOD Receive bit rate period 2 Where Receive bit rate period is the period of the input bit rate 10 6 2 Switching Latency Switching latency is the time it ...

Page 134: ...ta TXPERIOD SYSPERIOD ESDATA T T T 23 4 External port to External port External port write enable to external port not empty flag SYSPERIOD EEDATA T T 5 10 6 4 Time code Latency The maximum time taken to propagate a time code through a routing switch SpaceWire port to SpaceWire port Last bit of time code into receiver to last bit of time code out of transmitter worst case where transmitter has sta...

Page 135: ...jitter measurements when the transmit bit rate and receive bit rate are 200M bits s Table 10 6 SpaceWire Router Latency and Jitter Measurements Bit rate 200Mbits s Description Symbol Value Units Switching Latency TSWITCH 133 3 ns max Router Latency SpaceWire to SpaceWire port TSSDATA 546 6 ns max Router Latency SpaceWire to External port TSEDATA 316 6 ns max Router Latency External to SpaceWire po...

Page 136: ...IF is not active clock and LVDS drivers switched off assume a reduction of POP by POP POFF x 0 1 0 06 Example 2 SpW interfaces deactivated at 200 Mb s Operational power 3 7 3 7 1 6 x 0 1 0 06 x 2 3 16 W max 2 For the data rates 200 Mb s the setting for the lowest power consumption i e lowest PLL and Tx clock frequency is assumed 3 The actual data flow has a negligible influence on the power consum...

Page 137: ...to 10 mA IIN Power pin 60 to 60 mA Lead temperature soldering 10 sec 300 C Ts Storage temperature range 65 to 150 C TJ Maximum junction temperature 175 C 11 3 RELIABILITY INFORMATION The information required for reliability analysis of the SpW 10X device has been collated and is presented in Table 11 3 Table 11 3 Reliabilty Information Parameter Value Technology CMOS 0 35 µm gate array Complexity ...

Page 138: ...ELINES In this section an example circuit diagram is provided and PCB and design guidelines presented 12 1 EXAMPLE CIRCUIT DIAGRAM A schematic showing how the SpW 10X device should be connected is provided on the following page This is a complete schematic for a stand alone router except for the 3 3V power supply and reset signal ...

Page 139: ...Ref UoD_SpW 10X_ UserManual Issue 3 4 SpW 10X SpaceWire Router User Manual Date 11th July 2008 Preliminary 139 ...

Page 140: ...d TestEn shall both be tied directly to the ground plane 12 2 4 Power and Decoupling 1 Each power pin shall be decoupled to ground using a 100 nF decoupling capacitor 2 The 100 nF decoupling capacitors shall be fitted close to the each power pin with the other end of the capacitor connected to the ground plane 3 In addition to the 100 nF decoupling capacitors four 1 µF decoupling capacitors shall ...

Page 141: ...ength 2 The series termination resistors should be placed as close as possible to the output pins of the SpW 10X device 3 Series termination resistors are also recommended on the devices driving the External FIFO port inputs if the tracks connected to the inputs are more than 4 cm in length 4 The pull up down resistor recommendations provided in section 5 3 should be followed 12 2 8 Time code Inte...

Page 142: ...llowing layout recommendations apply to the PLL circuitry 1 To minimize voltage parasitic through ground the loop filter and VCO bias components will have a separate ground plane underneath all PLL pins and components 2 This PLL ground plane shall be connected at one point to the PLLVSS pad 3 To minimize other electromagnetic crosstalk effects SMD components should be used and placed as close as p...

Page 143: ...ey are all gathered in this section for convenience WARNING Simultaneous data strobe transitions can occur during reset and power up This is not a problem when connected to SpaceWire compliant devices but is a problem when connected to IEEE 1355 devices WARNING Since LVDS is based on a current loop it should not matter what the supply voltage is to an LVDS device connected to the SpW 10X router Ho...

Page 144: ...ed to have Stat_mux_out 4 pulled low by default in order to enable the watchdog timers on reset WARNING When the watchdog timers are not enabled the SpaceWire and external ports can block indefinitely if for example a source stops sending data in the middle of a packet If watchdog timers are not enabled then it must be possible for a network manager to detect blocking situations and to reset the r...

Page 145: ...hen watchdog timer mode set see section 8 3 5 and the packet will be spilt If the packet is a small packet it could continually circle around the loop A SpaceWire network architecture and configuration should be checked for possible loops for all logical addresses being used Unused logical addresses should NOT be configured in the SpW 10X routing tables so that a packet arriving at a router with a...

Page 146: ... data and strobe see Figure 13 3 A simultaneous transition or glitch on data and strobe may occur when reset is released Figure 13 4 Figure 13 1 Reset Waveform Figure 13 2 Reset Waveform with Data and Strobe Both High Figure 13 3 Glitches on Data or Strobe during Reset Figure 13 4 Simultaneous Transition of Data and Strobe during Reset ...

Page 147: ... recommended that the old devices are replaced by the new SpaceWire compliant SMCS332SpW and SMCS116SpW devices which are or shortly will be available from Atmel If operation with legacy units which use IEEE 1355 devices is necessary and these devices cannot be replaced by the new SpaceWire compliant parts then the following reset sequence is recommended 1 Assert the reset for the SpW 10X device 2...

Page 148: ...the input bit rate higher input bit rates result in more received characters being appended to the buffer after the parity error The maximum time to reset the receiver after detecting the parity error is 167 ns Therefore if no data characters are input for 167 ns after the parity error no extra data characters are inserted to the receive buffer If the input link rate is below 24 Mbit s the anomaly...

Page 149: ...cific workaround for this anomaly as a similar situation can occur in any case when an error on a link does not cause an immediate parity error but one is produced in a subsequence character To avoid this causing a problem with a SpaceWire application it is important to include additional integrity checks in critical SpaceWire packets This approach should also be used to mitigate the effects of th...

Page 150: ...port for the SpW 10X Router is provided by STAR Dundee Ltd A range of SpW 10X evaluation boards is available along with other test equipment cables etc See www star dundee com for details Technical support is provided by STAR Dundee All requests for support should be submitted to the Atmel support hotline Email assp applab hotline nto atmel com ...

Page 151: ...ted 15 2 ISSUE 3 2 TO ISSUE 3 3 Section Ref Change 1 2 Table 1 2 RD3 changed to more appropriate reference document that includes information on LVDS 8 1 5 Figure 8 3 Bias resistor value corrected to 20k ohms 9 3 Table 9 3 The reset values of the GAR bits are undefined after power on and unchanged after reset except the Invalid Address bit which is 1 after power on or reset 12 2 6 Point 1 Editoria...

Page 152: ... 3 Section added to give more details on reset anomaly 15 4 ISSUE 3 0 TO ISSUE 3 1 Section Ref Change 5 6 Second warning clarified 7 6 10 Note added explaining that command packet fill bytes is a feature of the SpW 10X and not of RMAP 8 1 6 13 2 Warning on setting data rate to less than 2 Mbits s deleted The SpW 10X device will not allow a TXDIV and TXRATE to be set to give a transmit data rate be...

Page 153: ...le Add Atmel part number as a reference 3 2 External Ports Add depth of external port FIFOs 5 2 SpaceWire Signals Rename data strobe IOs so the naming is consistent in the document Note pin names should map to pin names in the data sheet therefore use Plus Minus notation 5 7 Power Ground PLL and LVDS Signals Additional information on power pins and PLL power supply circuitry 10 3 Group Adaptive Ro...

Page 154: ...UE 1 6 TO ISSUE 1 7 Section Ref Change All Corrections added following validation 15 13 ISSUE 1 5 TO ISSUE 1 6 Section Ref Change 8 RMAP section added 15 14 ISSUE 1 4 TO ISSUE 1 5 Section Ref Change All Footer changed to indicate preliminary and a note added on the front page to indicate that section 8 6 is subject to change 15 15 ISSUE 1 3 TO ISSUE 1 4 Section Ref Change 7 Latency and jitter spec...

Page 155: ...g data added 15 18 ISSUE 1 0 TO ISSUE 1 1 Section Ref Change 5 1 Table 5 1 FEEDBDIV PLL clock settings section added 5 5 Table 5 5 STAT_MUX_OUT changed to multi function pin 5 6 Table 5 6 Power on reset signals mapped to STAT_MUX_OUT pins 8 1 6 Setting the data rate takes account of FEEDBDIV and transmit clock control register setting TXDIV 8 3 5 Packet blocking correction does not cause disconnec...

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