610
11054A–ATARM–27-Jul-11
SAM9X25
• Block-oriented commands: These commands send a data block succeeded by CRC bits.
Both read and write operations allow either single or multiple block transmission. A multiple
block transmission is terminated when a stop command follows on the CMD line similarly to the
sequential read or when a multiple block transmission has a pre-defined block count (
Transfer Operation” on page 613.
The HSMCI provides a set of registers to perform the entire range of High Speed MultiMedia
Card operations.
34.8.1
Command - Response Operation
After reset, the HSMCI is disabled and becomes valid after setting the MCIEN bit in the
HSMCI_CR Control Register.
The PWSEN bit saves power by dividing the HSMCI clock by 2
PWSDIV
+ 1 when the bus is
inactive.
The two bits, RDPROOF and WRPROOF in the HSMCI Mode Register (HSMCI_MR) allow
stopping the HSMCI Clock during read or write access if the internal FIFO is full. This will guar-
antee data integrity, not bandwidth.
All the timings for High Speed MultiMedia Card are defined in the High Speed MultiMediaCard
System Specification.
The two bus modes (open drain and push/pull) needed to process all the operations are defined
in the HSMCI command register. The HSMCI_CMDR allows a command to be carried out.
For example, to perform an ALL_SEND_CID command:
The command ALL_SEND_CID and the fields and values for the HSMCI_CMDR Control Regis-
ter are described in
Note:
bcr means broadcast command with response.
Host Command
N
ID
Cycles
CID
CMD
S
T
Content
CRC
E
Z
******
Z
S
T
Content
Z
Z
Z
Table 34-6.
ALL_SEND_CID Command Description
CMD Index
Type
Argument
Resp
Abbreviation
Command
Description
CMD2
bcr
[31:0] stuff bits
R2
ALL_SEND_CID
Asks all cards to send
their CID numbers on
the CMD line
Table 34-7.
Fields and Values for HSMCI_CMDR Command Register
Field
Value
CMDNB (command number)
2 (CMD2)
RSPTYP (response type)
2 (R2: 136 bits response)
SPCMD (special command)
0 (not a special command)
OPCMD (open drain command)
1
MAXLAT (max latency for command to response)
0 (NID cycles ==> 5 cycles)
Summary of Contents for SAM9X25
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