501
11054A–ATARM–27-Jul-11
SAM9X25
501
11054A–ATARM–27-Jul-11
SAM9X25
31.6
Write Protection Registers
To prevent any single software error that may corrupt DMAC behavior, the DMAC address
space can be write-protected by setting the WPEN bit in the
“DMAC Write Protect Mode Regis-
If a write access to anywhere in the DMAC address space is detected, then the WPVS flag in the
DMAC Write Protect Status Register (MCI_WPSR) is set and the field WPVSRC indicates in
which register the write access has been attempted.
The WPVS flag is reset by writing the DMAC Write Protect Mode Register (DMAC_WPMR) with
the appropriate access key, WPKEY.
The protected registers are:
•
“DMAC Global Configuration Register” on page 503
•
“DMAC Enable Register” on page 504
•
“DMAC Channel x [x = 0..7] Source Address Register” on page 514
•
“DMAC Channel x [x = 0..7] Destination Address Register” on page 515
•
“DMAC Channel x [x = 0..7] Descriptor Address Register” on page 516
•
“DMAC Channel x [x = 0..7] Control A Register” on page 517
•
“DMAC Channel x [x = 0..7] Control B Register” on page 519
•
“DMAC Channel x [x = 0..7] Configuration Register” on page 521
•
“DMAC Channel x [x = 0..7] Source Picture in Picture Configuration Register” on page 523
•
“DMAC Channel x [x = 0..7] Destination Picture in Picture Configuration Register” on page
524
Summary of Contents for SAM9X25
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Page 138: ...138 11054A ATARM 27 Jul 11 SAM9X25 138 11054A ATARM 27 Jul 11 SAM9X25...
Page 162: ...162 11054A ATARM 27 Jul 11 SAM9X25 162 11054A ATARM 27 Jul 11 SAM9X25...
Page 216: ...216 11054A ATARM 27 Jul 11 SAM9X25 216 11054A ATARM 27 Jul 11 SAM9X25...
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Page 532: ...532 11054A ATARM 27 Jul 11 SAM9X25 532 11054A ATARM 27 Jul 11 SAM9X25...
Page 692: ...692 11054A ATARM 27 Jul 11 SAM9X25 692 11054A ATARM 27 Jul 11 SAM9X25...
Page 777: ...777 11054A ATARM 27 Jul 11 SAM9X25 777 11054A ATARM 27 Jul 11 SAM9X25...
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